Patents by Inventor Eric Nestler
Eric Nestler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8179731Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: May 15, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Patent number: 8107306Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: January 31, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Publication number: 20100220514Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 2, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds
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Publication number: 20100207644Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.Type: ApplicationFiled: August 21, 2009Publication date: August 19, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic
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Patent number: 7593256Abstract: Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit.Type: GrantFiled: March 28, 2007Date of Patent: September 22, 2009Assignee: Contour Semiconductor, Inc.Inventor: Eric Nestler
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Patent number: 7548453Abstract: Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.Type: GrantFiled: March 28, 2007Date of Patent: June 16, 2009Assignee: Contour Semiconductor, Inc.Inventor: Eric Nestler
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Patent number: 7548454Abstract: Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.Type: GrantFiled: March 28, 2007Date of Patent: June 16, 2009Assignee: Contour Semiconductor, Inc.Inventor: Eric Nestler
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Publication number: 20080079708Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuitsType: ApplicationFiled: September 28, 2007Publication date: April 3, 2008Inventors: Abhishek Bandyopadhyay, Eric Nestler, Michael Ashburn
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Publication number: 20070253234Abstract: Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.Type: ApplicationFiled: March 28, 2007Publication date: November 1, 2007Inventor: Eric Nestler
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Publication number: 20070242494Abstract: Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.Type: ApplicationFiled: March 28, 2007Publication date: October 18, 2007Inventor: Eric Nestler
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Publication number: 20070230243Abstract: Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit.Type: ApplicationFiled: March 27, 2007Publication date: October 4, 2007Inventor: Eric Nestler
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Patent number: 6916603Abstract: The present invention is based on the discovery that overexpression of ?FosB leads to bone formation and that ?FosB expression inhibits adipogenesis. The present invention provides methods of identifying agents that modulate bone formation and adipogenesis. Moreover, the present invention provides methods for identifying genes that are modulated by ?FosB and that modulates ?FosB, osteogenesis, and adipogenesis.Type: GrantFiled: August 28, 2001Date of Patent: July 12, 2005Assignee: Yale UniversityInventors: Roland E. Baron, Natalie Sims, Georgios Sabatakos, Eric Nestler, Jingshan Chen, Max Kelz
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Patent number: 6879274Abstract: An analog-to-digital metering circuit includes a first programmable gain amplifier to amplify a first voltage signal from a first channel before being received by a first analog-to-digital converter that converts the amplified first voltage signal to a first digital signal. A second programmable gain amplifier amplifies a second voltage signal from a second channel and feds the amplified signal to a second analog-to-digital converter that converts the amplified second voltage signal to a second digital signal. A first lowpass filter circuit receives the first and second digital signals, to generate therefrom, a multi-bit analog-to-digital value. A direct digital synthesizer generates a digital signal representing a predetermined waveform that is fed to a digital-to-analog converter. The second voltage signal and the digital signal representing the predetermined waveform are multiplied together to generate a digital value.Type: GrantFiled: February 24, 2004Date of Patent: April 12, 2005Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Paul Daigle, Michael A. Ashburn, Jr.
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Publication number: 20040252043Abstract: An analog-to-digital metering circuit includes a first programmable gain amplifier to amplify a first voltage signal from a first channel before being received by a first analog-to-digital converter that converts the amplified first voltage signal to a first digital signal. A second programmable gain amplifier amplifies a second voltage signal from a second channel and feds the amplified signal to a second analog-to-digital converter that converts the amplified second voltage signal to a second digital signal. A first lowpass filter circuit receives the first and second digital signals, to generate therefrom, a multi-bit analog-to-digital value. A direct digital synthesizer generates a digital signal representing a predetermined waveform that is fed to a digital-to-analog converter. The second voltage signal and the digital signal representing the predetermined waveform are multiplied together to generate a digital value.Type: ApplicationFiled: February 24, 2004Publication date: December 16, 2004Inventors: Eric Nestler, Paul Daigle, Michael A. Ashburn
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Patent number: 6781361Abstract: A power metering system including a first modulator receiving a first analog voltage associated with a current and outputting a first digitized signal. A second modulator receives a second analog voltage and outputs a second digitized signal. A first lowpass filter filters out high frequency noise associated with the first signal and decimates the frequency of the first digitized signal. The first lowpass filter outputs a first filtered signal. An interpolator performs up sampling of the signal associated with the first filtered signal. The interpolator outputs a first up sampled signal. An integrator integrates the first up sampled signal. The integrator outputs an integrated signal. A first multiplier multiplies the second digitized signal and integrated signal, and outputs a multiplied signal. The multiplied signal being used to measure power.Type: GrantFiled: April 26, 2002Date of Patent: August 24, 2004Assignee: Analog Devices, Inc.Inventor: Eric Nestler
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Publication number: 20020175671Abstract: A power metering system including a first modulator receiving a first analog voltage associated with a current and outputting a first digitized signal. A second modulator receives a second analog voltage and outputs a second digitized signal. A first lowpass filter filters out high frequency noise associated with the first signal and decimates the frequency of the first digitized signal. The first lowpass filter outputs a first filtered signal. An interpolator performs up sampling of the signal associated with the first filtered signal. The interpolator outputs a first up sampled signal. An integrator integrates the first up sampled signal. The integrator outputs an integrated signal. A first multiplier multiplies the second digitized signal and integrated signal, and outputs a multiplied signal. The multiplied signal being used to measure power.Type: ApplicationFiled: April 26, 2002Publication date: November 28, 2002Inventor: Eric Nestler
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Publication number: 20020077273Abstract: The present invention is based on the discovery that overexpression of &Dgr;FosB leads to bone formation and that &Dgr;FosB expression inhibits adipogenesis. The present invention provides methods of identifying agents that modulate bone formation and adipogenesis. Moreover, the present invention provides methods for identifying genes that are modulated by &Dgr;FosB and that modulates &Dgr;FosB, osteogenesis, and adipogenesis.Type: ApplicationFiled: August 28, 2001Publication date: June 20, 2002Inventors: Roland E. Baron, Natalie Sims, Geogios Sabatakos, Eric Nestler, Jingshan Chen, Max Kelz
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Patent number: 6307493Abstract: Apparatus, and method, for producing a signal representative of a non-linear function of an input signal. The apparatus includes a feedback loop having a sigma-delta modulator fed by the input signal and a feedback signal, such feedback signal being a non-linear function of the output of the modulator. The output of the sigma-delta modulator is a stream of m-bit digital words. The output of the sigma-delta modulator is fed to an filter for converting the stream of m-bit digital words produced by the sigma-delta modulator into a corresponding stream of n-bit digital words. The n-bit and m-bit streams of digital words are fed to a multiplier. The multiplier produces an series of digital words, each one of the digital words representing the product of one of the n-bit digital words and a one of the n-bit digital words. The series of digital words produced by the multiplier is fed to the sigma-delta modulator as the feedback signal.Type: GrantFiled: May 28, 1999Date of Patent: October 23, 2001Assignee: Analog Devices, Inc.Inventor: Eric Nestler
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Patent number: 6278392Abstract: A system having an adjustable gain includes: a modulator, for producing a stream of digital words representative of an input analog signal; and, a gain adjustor, fed by a gain signal representative of the adjustable gain, for converting the stream of digital words produced by modulator into an output stream of bits representative of the gain adjusted input analog signal. The stream of stream of digital words produced by modulator, which represent the gain adjusted input analog signal, can be produced with an register for storing the gain signal and an adder. Further, the stream of digital words bits produced by modulator can fed to an compact sinc filter for conversion into digital words which represent digital samples on the gain adjusted input analog signal. The system includes a sigma-delta modulator for producing a stream of digital words having values, M or N, such stream of digital words bits being representative of an input analog signal, X(t) fed to the modulator.Type: GrantFiled: August 10, 1999Date of Patent: August 21, 2001Assignee: Analog Devices, Inc.Inventor: Eric Nestler
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Patent number: 5917689Abstract: An apparatus and method for protecting integrated circuits from electrical overstress and eletrostatic discharge is provided. The apparatus includes a primary EOS/ESD protection device and a feedback circuit. The feedback circuit maintain the primary EOS/ESD protection device in an off state during normal operation of the integrated circuit and switches the primary protection device to an state when an EOS/ESD event occurs at a first input pad with respect to a second input pad of the integrated circuit.Type: GrantFiled: September 12, 1996Date of Patent: June 29, 1999Assignee: Analog Devices, Inc.Inventors: Stephen T. English, Eric Nestler, Andrew H. Olney