Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.

Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

Abstract: A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.

Abstract: Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.

Abstract: A centrifugal separator for the separation a slurry into a light phase fraction and a heavy phase fraction including a rotatable shell having a cylindrical portion and a conical portion with a rotatable auger therein and a light phase opening at one end and a heavy phase opening at a second end sized to throttle the flow of light phase liquid and heavy phase liquid and sized in the cross-sectional area ratio of A/B so that the discharge from the separator will continue to be in the ratio of A/B regardless of throughput and in one form the separator has a second heavy phase opening in the cylindrical portion and in another form, an annular barrier vane on the auger blocking flow of liquid fraction toward the heavy fraction opening.

Abstract: A method for operating and improving the throughput and efficiency of a worm centrifuge by introducing, at a controlled frequency, successive pressure surges into the concentrated sludge fraction within the bowl separator preceding the solids discharge opening whereby the pulse frequency and the level of pressure are controllable and can be controlled as a function of the sludge fraction throughput through the separator.