Abstract: A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to individual memory sections of a semiconductor memory array. Individual sections of memory are isolated from a fixed power supply by inserting one or more NFETs and diodes between GND and a negative connection of an individual memory section. The voltage applied to each memory section is controlled by applying a separate variable voltage to each gate of all NFETs connected to a particular memory section. If a memory section is not accessed, the voltage to that section can be lowered, saving power. If a memory section is accessed, the voltage to that section may be raised, providing more power and shortening read and write times.

Abstract: An a new dynamic logic entry latch or new “ELAT” and a method to capture a static input and convert it to a single rail dynamic signal with improved functionality and reduced clock and input load. The new ELAT utilizes a pulsed evaluate concept to enable more complex pull-down stack configurations and other improvements. The pulsed evaluate concept uses a pulse generators driven by the static input and a clock waveform to evaluate the static input and appropriately drive field effect transmitters on the pull-down stack. Utilizing multiple-input pulse generators or multiple pulse generators, the new ELAT can allow a wider variety of input functions and their inverses to be constructed without over-loading the pull-down stack.

Abstract: An integrated circuit chip responds to clock waves having differing frequencies at different times. The chip includes a semiconductor memory cell having a write enable input terminal responsive to a write enable signal having first and second levels. The cell has a tendency to operate improperly in response to the first level of the write enable signal having an excessively long predetermined duration. A write enable signal source responds to the clock waves so that for clock waves having half cycles of duration less than the predetermined duration the first level of the write enable signal has durations approximately equal to the durations of the half cycles of these clock waves. For clock waves having half cycles of duration greater than the predetermined duration, the first level of the write enable signal has a duration substantially equal to the predetermined duration.