Patents by Inventor Eric Stave
Eric Stave has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7274606Abstract: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle.Type: GrantFiled: November 9, 2006Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Eric Stave
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Publication number: 20070058460Abstract: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle.Type: ApplicationFiled: November 9, 2006Publication date: March 15, 2007Inventor: Eric Stave
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Patent number: 7167401Abstract: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle.Type: GrantFiled: February 10, 2005Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventor: Eric Stave
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Publication number: 20060253738Abstract: A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, may be transferred from the integrated circuit of the electronic device to an external processor using the device's ODT circuit instead of the output data signal driver circuit. Therefore, no capacitive loading of output drivers occurs during test mode operations. Thus the speed of the output data path (i.e., the circuit path propagating non-test mode related signals from the electronic device to other external units in the system) is not affected by test mode operations, allowing a system designer to increase the speed of the data output path as much as desired. Further, deterioration in the quality of signals output from the output drivers is also avoided.Type: ApplicationFiled: July 13, 2006Publication date: November 9, 2006Inventor: Eric Stave
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Publication number: 20060176744Abstract: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle.Type: ApplicationFiled: February 10, 2005Publication date: August 10, 2006Inventor: Eric Stave
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Publication number: 20050283671Abstract: A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, may be transferred from the integrated circuit of the electronic device to an external processor using the device's ODT circuit instead of the output data signal driver circuit. Therefore, no capacitive loading of output drivers occurs during test mode operations. Thus the speed of the output data path (i.e., the circuit path propagating non-test mode related signals from the electronic device to other external units in the system) is not affected by test mode operations, allowing a system designer to increase the speed of the data output path as much as desired. Further, deterioration in the quality of signals output from the output drivers is also avoided.Type: ApplicationFiled: June 21, 2004Publication date: December 22, 2005Inventor: Eric Stave
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Patent number: 6002623Abstract: A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.Type: GrantFiled: January 22, 1999Date of Patent: December 14, 1999Assignee: Micron Technology, Inc.Inventors: Eric Stave, Phillip G. Wald
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Patent number: 5892720Abstract: A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.Type: GrantFiled: October 27, 1997Date of Patent: April 6, 1999Assignee: Micron Technology, Inc.Inventors: Eric Stave, Phillip G. Wald
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Patent number: 5684809Abstract: A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.Type: GrantFiled: February 12, 1997Date of Patent: November 4, 1997Assignee: Micron Technology, Inc.Inventors: Eric Stave, Phillip G. Wald