Patents by Inventor Eric Tan Swee Seng

Eric Tan Swee Seng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6951982
    Abstract: Various aspects of the invention provide microelectronic component assemblies, memory modules, computer systems, and methods of assembling microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a non-leaded first package, a second package, and a plurality of electrical junctions. The first package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces. The second package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces of a number of leads. Each of the junctions couples one of the contacts to the contact surface of one of the leads. The electrical junctions may also physically support the packages with their respective confronting surfaces juxtaposed with but spaced from one another, defining a peripherally open fluid passage and enhancing thermal performance.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: October 4, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Lim Thiam Chye, Setho Sing Fee, Eric Tan Swee Seng
  • Patent number: 6943450
    Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: September 13, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Setho Sing Fee, Lim Thiam Chye, Eric Tan Swee Seng
  • Patent number: 6876066
    Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Setho Sing Fee, Lim Thiam Chye, Eric Tan Swee Seng
  • Publication number: 20040217459
    Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 4, 2004
    Inventors: Setho Sing Fee, Lim Thiam Chye, Steven W. Heppler, Leng Nam Yin, Keith Tan, Patrick Guay, Edmund Lua Koon Tian, Yap Kah Eng, Eric Tan Swee Seng
  • Patent number: 6746894
    Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: June 8, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Setho Sing Fee, Lim Thiam Chye, Steven W. Heppler, Leng Nam Yin, Keith Tan, Patrick Guay, Edmund Lua Koon Tian, Yap Kah Eng, Eric Tan Swee Seng
  • Publication number: 20040100772
    Abstract: Various aspects of the invention provide microelectronic component assemblies, memory modules, computer systems, and methods of assembling microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a non-leaded first package, a second package, and a plurality of electrical junctions. The first package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces. The second package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces of a number of leads. Each of the junctions couples one of the contacts to the contact surface of one of the leads. The electrical junctions may also physically support the packages with their respective confronting surfaces juxtaposed with but spaced from one another, defining a peripherally open fluid passage and enhancing thermal performance.
    Type: Application
    Filed: December 18, 2002
    Publication date: May 27, 2004
    Inventors: Lim Thiam Chye, Setho Sing Fee, Eric Tan Swee Seng
  • Publication number: 20030042581
    Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Setho Sing Fee, Lim Thiam Chye, Eric Tan Swee Seng
  • Publication number: 20020142513
    Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.
    Type: Application
    Filed: April 19, 2001
    Publication date: October 3, 2002
    Inventors: Setho Sing Fee, Lim Thiam Chye, Steven W. Heppler, Leng Nam Yin, Keith Tan, Patrick Guay, Edmund Lua Koon Tian, Yap Kah Eng, Eric Tan Swee Seng