Abstract: Embodiments of the present invention provide an approach that utilizes discrete event simulation to quantitatively analyze the reliability of a modeled de-duplication system in a computer storage environment. In addition, the approach described herein can perform such an analysis on systems having heterogeneous data stored on heterogeneous storage systems in the presence of primary faults and their secondary effects due to de-duplication. In a typical embodiment, data de-duplication parameters and a hardware configuration are received in a computer storage medium. A data de-duplication model is then applied to a set of data and to the data de-duplication parameters, and a hardware reliability model is applied to the hardware configuration. Then a set (at least one) of discrete events is simulated based on the data de-duplication model as applied to the set of data and the data de-duplication parameters, and the hardware reliability model as applied to the hardware configuration.

Abstract: Embodiments of the present invention provide an approach that utilizes discrete event simulation to quantitatively analyze the reliability of a modeled de-duplication system in a computer storage environment. In addition, the approach described herein can perform such an analysis on systems having heterogeneous data stored on heterogeneous storage systems in the presence of primary faults and their secondary effects due to de-duplication. In a typical embodiment, data de-duplication parameters and a hardware configuration are received in a computer storage medium. A data de-duplication model is then applied to a set of data and to the data de-duplication parameters, and a hardware reliability model is applied to the hardware configuration. Then a set (at least one) of discrete events is simulated based on the data de-duplication model as applied to the set of data and the data de-duplication parameters, and the hardware reliability model as applied to the hardware configuration.

Abstract: A circuit (10) for transferring power delivered to a load (16) from a primary voltage source (12) to a secondary power source (14) uses three transistors (32, 40, 46) which switch whenever there is a loss of power from the primary source (12). A capacitor (36), interposed between the first transistor (32) and the second transistor (40) attenuates the signal from the first transistor (32) after a predetermined amount of time to switch the second and third transistors (40,46) to isolate the load (16) from the secondary power source (14).