Abstract: A system has an input voltage source, a power stage coupled to the input voltage source, a load coupled to an output node of the power stage and a control circuit, the control circuit implemented on a semiconductor die and including: an error amplifier having a first input, a second input and an output; a voltage divider coupled to the output node and configured to provide an output voltage sense value to the first input of the error amplifier; and a programmable reference voltage circuit with an output coupled to the second input of the error amplifier. The programmable reference voltage circuit includes: a reference voltage source; scaling circuit components between the reference voltage source and the second input of the error amplifier; and a switch between the reference voltage source and the second input of the error amplifier. The control circuit is coupled to the power stage and is configured to generate a control signal for switches of the power stage.

Abstract: A system has an input voltage source, a power stage coupled to the input voltage source, a load coupled to an output node of the power stage and a control circuit, the control circuit implemented on a semiconductor die and including: an error amplifier having a first input, a second input and an output; a voltage divider coupled to the output node and configured to provide an output voltage sense value to the first input of the error amplifier; and a programmable reference voltage circuit with an output coupled to the second input of the error amplifier. The programmable reference voltage circuit includes: a reference voltage source; scaling circuit components between the reference voltage source and the second input of the error amplifier; and a switch between the reference voltage source and the second input of the error amplifier. The control circuit is coupled to the power stage and is configured to generate a control signal for switches of the power stage.

Abstract: An SMPS current mode control loop with an adjusted cycle-by-cycle peak current limit for buck and boost (and bidirectional buck/boost) regulators. An SMPS regulator can include a PWM driver to drive switching control signals with a PWM duty cycle to an output terminal OUT, and a PWM controller to control the PWM duty cycle based on a current mode control loop that includes slope compensation to provide a signal VPK corresponding to a current sense signal from a current sense terminal CS, based on sensed peak current through the energy storage element, superimposed with an injected slope compensation current corresponding to a predefined slope compensation based on PWM duty cycle.

Abstract: An SMPS current mode control loop with an adjusted cycle-by-cycle peak current limit for buck and boost (and bidirectional buck/boost) regulators. An SMPS regulator can include a PWM driver to drive switching control signals with a PWM duty cycle to an output terminal OUT, and a PWM controller to control the PWM duty cycle based on a current mode control loop that includes slope compensation to provide a signal VPK corresponding to a current sense signal from a current sense terminal CS, based on sensed peak current through the energy storage element, superimposed with an injected slope compensation current corresponding to a predefined slope compensation based on PWM duty cycle.