Abstract: A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.

Abstract: A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.