Abstract: The present invention provides for calibrating a TSRO with two tests, wherein generating a first or second calibration value does not substantially alter the temperature performed within the first or second test. The first calibration value is generated during a first test at a first temperature. The first test can be a wafer test, a module test, a burn-in test, and so on. The first calibration value is stored with an e-fuse in the integrated circuit. A second calibration value is generated during a second integrated circuit test of the integrated circuit at a second temperature. The second test can be a test that is performed at a temperature other than the first test. The second calibration value is stored with an e-fuse in the integrated circuit.

Abstract: A method for making a structure for bonding to a conductive pad on a semiconductor substrate is described. The structure comprises a glassy passivating layer with a thickness of at least 3 microns deposited over the conductive pad. The passivating layer defines an aperture which exposes a portion of the conductive pad. A metal bump covers the portion of the conductive pad exposed in the aperture and further extends over the edges of the glassy passivating layers so as to form a seal between the conductive pad and the glassy passivating layer. A subsequent thermal compression bonding operation on such structure does not cause fractures in the glassy passivating layer due to its thickness.

Abstract: A structure for bonding to a conductive pad on a semiconductor substrate is described. The structure comprises a glassy passivating layer with a thickness of at least 3 microns deposited over the conductive pad. The passivating layer defined an aperture which exposes a portion of the conductive pad. A metal bump covers the portion of the conductive pad exposed in the aperture and further extends over the edges of the glassy passivating layer so as to form a seal between the conductive pad and the glassy passivating layer. A subsequent thermal compression bonding operation on such structure does not cause fractures in the glassy passivating layer due to its thickness.

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).

Abstract: Heat is removed from a Large Scale Integrated Circuit semiconductor package via a thermal conductive path including a thermally conductive liquid. The integrated circuit chips are flip chip bonded to a substrate having a printed circuit and raised contact pads serving to interconnect contact areas on the chip. A metal, ceramic (or combination thereof) cover engages the perimeter of the substrate and encloses the chips (or chip). The thermal liquid is contained within the cavity define by the cover and substrate. The chips (or chip) and the flip chip connections are protected from contamination and the deleterious effects of the thermally conductive liquid by a parylene film enveloping same. Additionally, back side bonded (beam lead) integrated circuit chips will have an enhanced heat transfer path by incorporating liquid metal and a protective coating of parylene.