Patents by Inventor Erich Boleyn
Erich Boleyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315462Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315445Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315455Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315460Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315459Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315461Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315572Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315444Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Patent number: 9058183Abstract: Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.Type: GrantFiled: December 29, 2009Date of Patent: June 16, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Thomas R. Woller, Patryk Kaminski, Erich Boleyn, Keith A. Lowery, Benjamin C. Serebrin
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Patent number: 8719543Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: GrantFiled: December 29, 2009Date of Patent: May 6, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Patryk Kaminski, Thomas Woller, Keith Lowery, Erich Boleyn
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Patent number: 8244978Abstract: Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).Type: GrantFiled: February 17, 2010Date of Patent: August 14, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Andrew Kegel, Mark Hummel, Erich Boleyn
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Publication number: 20110202724Abstract: Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Andrew G. KEGEL, Mark Hummel, Erich Boleyn
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Publication number: 20110161955Abstract: Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Inventors: Thomas R. Woller, Patryk Kaminski, Erich Boleyn, Keith A. Lowery, Benjamin C. Serebrin
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Publication number: 20110161620Abstract: Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Patryk KAMINSKI, Thomas WOLLER, Keith LOWERY, Erich BOLEYN
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Publication number: 20110161619Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Patryk KAMINSKI, Thomas WOLLER, Keith LOWERY, Erich BOLEYN
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Publication number: 20110107328Abstract: A data processing device is configured such that, during a loop executed by a guest, the device executes a PAUSE instruction. In response to executing a PAUSE instruction, the data processing device determines a relationship between the current PAUSE instruction and a previously executed PAUSE instruction. For example, the data processing device can determine the amount of time that has elapsed between the PAUSE instructions. Based on the relationship between the current and previous pause instructions, the data processing device can reset the counter to a reset value, or adjust (i.e. increment or decrement) the counter by a defined amount.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Benjamin C. Serebrin, David S. Christie, Erich Boleyn, Michael P. Hohmuth
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Patent number: 7318141Abstract: Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.Type: GrantFiled: December 17, 2002Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Steve M. Bennett, Gilbert Neiger, Erik C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Richard A. Uhlig, Larry Smith, Dion Rodgers, Andrew Glew, Erich Boleyn
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Publication number: 20040117539Abstract: Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.Type: ApplicationFiled: December 17, 2002Publication date: June 17, 2004Applicant: Intel CorporationInventors: Steve M. Bennett, Gilbert Neiger, Erik C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Richard A. Uhlig, Larry Smith, Dion Rodgers, Andrew Glew, Erich Boleyn