Patents by Inventor Erich Preiner

Erich Preiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11877388
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component embedded in the stack, and a functional film covering at least part of the component and having an inhomogeneous thickness distribution over at least part of a surface of the component.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 16, 2024
    Assignee: AT&SAustria Technologie & Systemtechnik AG
    Inventors: Imane Souli, Vanesa López Blanco, Erich Preiner, Martin Schrei
  • Patent number: 11683884
    Abstract: A component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and having a cavity delimited at least partially by a first polymer, and a component embedded in the cavity of the stack and being at least partially covered by a second polymer, wherein an anchoring interface is formed at an interface between the first polymer and the second polymer at which the first polymer and the second polymer are mechanically anchored with each other.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 20, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Imane Souli, Erich Preiner, Martin Schrei, Vanesa López Blanco
  • Patent number: 11570904
    Abstract: A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 31, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik
    Inventors: Wolfgang Schrittwieser, Mike Morianz, Alexander Kasper, Erich Preiner, Thomas Krivec
  • Publication number: 20220181243
    Abstract: A method for manufacturing a component carrier is disclosed. The method includes the steps of providing a layer stack having at least one component carrier material, forming a photoimageable dielectric layer structure on the layer stack, forming a spatial pattern of an electrically conductive layer structure on the photoimageable dielectric layer structure, wherein the spatial pattern defines openings formed within the electrically conductive layer structure, and exposing the photoimageable dielectric layer structure to electromagnetic radiation, where the spatial pattern of the electrically conductive layer structure represents a mask for selectively exposing predefined regions of the photoimageable dielectric layer structure. Furthermore, the method includes selectively removing material from the photoimageable dielectric layer depending on the spatial pattern.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventors: Marco Gavagnin, Erich Preiner, Hyung Park
  • Publication number: 20210400803
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component embedded in the stack, and a functional film covering at least part of the component and having an inhomogeneous thickness distribution over at least part of a surface of the component.
    Type: Application
    Filed: March 31, 2021
    Publication date: December 23, 2021
    Inventors: Imane Souli, Vanesa López Blanco, Erich Preiner, Martin Schrei
  • Publication number: 20210400808
    Abstract: A component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and having a cavity delimited at least partially by a first polymer, and a component embedded in the cavity of the stack and being at least partially covered by a second polymer, wherein an anchoring interface is formed at an interface between the first polymer and the second polymer at which the first polymer and the second polymer are mechanically anchored with each other.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 23, 2021
    Inventors: Imane Souli, Erich Preiner, Martin Schrei, Vanesa López Blanco
  • Publication number: 20200305286
    Abstract: A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.
    Type: Application
    Filed: April 6, 2020
    Publication date: September 24, 2020
    Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Wolfgang Schrittwieser, Mike Morianz, Alexander Kasper, Erich Preiner, Thomas Krivec
  • Patent number: 10645816
    Abstract: A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 5, 2020
    Assignee: AT&S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Wolfgang Schrittwieser, Mike Morianz, Alexander Kasper, Erich Preiner, Thomas Krivec
  • Publication number: 20200083154
    Abstract: A component carrier with a layer stack having at least one component carrier material and a photoimageable dielectric layer structure formed on top of the layer stack. The photoimageable dielectric layer structure has at least one recess extending vertically through the photoimageable dielectric layer structure. The at least one recess is formed by partially removing the photoimageable dielectric layer structure in regions which are defined by a spatial pattern of an electrically conductive layer structure formed on the photoimageable dielectric layer structure. The spatial pattern defines openings formed within the electrically conductive layer structure. A method for manufacturing such a component carrier is also described.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Marco Gavagnin, Erich Preiner, Hyung Wook Park
  • Publication number: 20160183383
    Abstract: A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.
    Type: Application
    Filed: June 23, 2014
    Publication date: June 23, 2016
    Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Wolfgang Schrittwieser, Mike Morianz, Alexander Kasper, Erich Preiner, Thomas Krivec