Patents by Inventor Erich Selna

Erich Selna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020166010
    Abstract: A computer system includes a primary chassis and a secondary chassis. The computer system further includes a primary device having a bus for carrying electrical signals and an external device having a bus for carrying electrical signals. The primary device is disposed in a primary chassis and the external device is disposed in the secondary chassis. The external device is directly electrically interconnected with the primary device so that the electrical signals carried on the primary device bus are transmitted to the secondary bus and the electrical signals carried on the external device bus are transmitted to the primary device bus. A method capable of sharing electrical signals includes transmitting a first electrical signal over a bus of a primary device disposed in a primary chassis and receiving the first electrical signal over a bus of an external device disposed in a secondary chassis.
    Type: Application
    Filed: May 1, 2001
    Publication date: November 7, 2002
    Applicant: Sun Microsystems, Inc
    Inventors: Erich Selna, Leesa Noujeim, Brian Verstegen
  • Publication number: 20020166019
    Abstract: A method for controlling a bus is provided. In particular, an external device may be interfaced with a bus internal to a computer system. The method involves detecting when a device is coupled to the bus, and driving signals onto the bus in response to detecting the device being coupled to the bus. Alternatively, when the external device is not coupled to the bus, the signals are blocked, disabled, or otherwise prevented from being delivered onto the bus.
    Type: Application
    Filed: May 1, 2001
    Publication date: November 7, 2002
    Inventors: Leesa Noujeim, Brian Verstegen, Erich Selna
  • Patent number: 5741729
    Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 21, 1998
    Assignee: Sun Microsystems, Inc.
    Inventor: Erich Selna
  • Patent number: 5650910
    Abstract: An electrical assembly which secures a detached cable/connector assembly to a substrate of a printed circuit board. The assembly has a printed circuit board that is mounted to a first surface of the substrate. The printed circuit board is coupled to an electrical connector assembly by a flexible cable. The electrical connector assembly can be plugged into an auxiliary device such as a CD-ROM. The electrical connector assembly has a tab that is inserted into an aperture located in the second surface of the substrate, to secure the connector assembly when the connector is not attached to the auxiliary device.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: July 22, 1997
    Assignee: Sun Microsystems, Inc.
    Inventors: Lee Winick, Kenneth Kitlas, Myra Torres, Erich Selna, Clifford B. Willis
  • Patent number: 5640048
    Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: June 17, 1997
    Assignee: Sun MicroSystems, Inc.
    Inventor: Erich Selna
  • Patent number: 5280409
    Abstract: An apparatus providing a heat sink and protective cover for a Tape Automated Bonding ("TAB") integrated circuit mounted on a printed circuit board. The apparatus is comprised of a printed circuit board with a plurality of thermal vias drilled through it. The TAB integrated circuit is mounted on the printed circuit board over the thermal vias. The vias draw then heat generated by the TAB integrated circuit to the other side of the printed circuit board. A heat sink is then placed over the thermal vias on the opposite side of the board to dissipate the heat. The heat sink is held in place by a spring clip which hooks onto a molded plastic cover placed over the TAB integrated circuit. The apparatus is easy to manufacture and efficiently dissipates the heat generated by TAB integrated circuits.
    Type: Grant
    Filed: October 9, 1992
    Date of Patent: January 18, 1994
    Assignee: Sun Microsystems, Inc.
    Inventors: Erich Selna, Ehsan Ettehadieh, James LaGassa