Patents by Inventor Erik Anthony LUCERO

Erik Anthony LUCERO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842973
    Abstract: A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: December 12, 2023
    Assignee: Google LLC
    Inventor: Erik Anthony Lucero
  • Publication number: 20230187401
    Abstract: A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventor: Erik Anthony Lucero
  • Patent number: 11574885
    Abstract: A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: February 7, 2023
    Assignee: Google LLC
    Inventor: Erik Anthony Lucero
  • Patent number: 11197365
    Abstract: A printed circuit board includes: multiple electrically insulating laminate sheets laminated together in a stack; a first electrically conductive layer formed from a superconductor material arranged on a first exterior surface of the stack, the first electrically conductive layer including a signal line and a ground plane; a second electrically conductive layer formed from a superconductor material arranged on a second exterior surface of the stack, the second exterior surface opposing the first exterior surface; a third conductive trace between a first electrically insulating laminate sheet of the stack and a directly adjacent second electrically insulating laminate sheet of the stack; a first via extending through from the signal line through the stack to the third conductive trace, in which the signal line is electrically connected to the third conductive trace through the via.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 7, 2021
    Assignee: Google LLC
    Inventor: Erik Anthony Lucero
  • Patent number: 11133451
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Patent number: 11133450
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Publication number: 20200176409
    Abstract: A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.
    Type: Application
    Filed: September 19, 2017
    Publication date: June 4, 2020
    Inventor: Erik Anthony Lucero
  • Publication number: 20200006621
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Application
    Filed: August 30, 2019
    Publication date: January 2, 2020
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Publication number: 20200006620
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Application
    Filed: August 30, 2019
    Publication date: January 2, 2020
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Patent number: 10497853
    Abstract: A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 3, 2019
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Patent number: 10468579
    Abstract: A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 5, 2019
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Publication number: 20190215952
    Abstract: A printed circuit board includes: multiple electrically insulating laminate sheets laminated together in a stack; a first electrically conductive layer formed from a superconductor material arranged on a first exterior surface of the stack, the first electrically conductive layer including a signal line and a ground plane; a second electrically conductive layer formed from a superconductor material arranged on a second exterior surface of the stack, the second exterior surface opposing the first exterior surface; a third conductive trace between a first electrically insulating laminate sheet of the stack and a directly adjacent second electrically insulating laminate sheet of the stack; a first via extending through from the signal line through the stack to the third conductive trace, in which the signal line is electrically connected to the third conductive trace through the via.
    Type: Application
    Filed: December 20, 2016
    Publication date: July 11, 2019
    Inventor: Erik Anthony Lucero
  • Publication number: 20180366634
    Abstract: A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.
    Type: Application
    Filed: December 30, 2015
    Publication date: December 20, 2018
    Inventors: Joshua Yousouf Mutus, Erik Anthony LUCERO