Patents by Inventor Erik English
Erik English has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979480Abstract: An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.Type: GrantFiled: September 20, 2022Date of Patent: May 7, 2024Assignee: International Business Machines CorporationInventors: Michael Sperling, Daniel Mark Dreps, Erik English, Jieming Qi
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Patent number: 11973630Abstract: An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.Type: GrantFiled: November 28, 2022Date of Patent: April 30, 2024Assignee: International Business Machines CorporationInventors: Michael B. Spear, Daniel Mark Dreps, Erik English, Jieming Qi, Michael Sperling
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Publication number: 20240121013Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Inventors: David J. KROLAK, Daniel Mark DREPS, Erik ENGLISH, Jieming QI, Michael SPERLING
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Publication number: 20240121072Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Inventors: David J. KROLAK, Daniel Mark DREPS, Erik ENGLISH, Jieming QI, Michael SPERLING
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Publication number: 20240097872Abstract: An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Michael Sperling, Daniel Mark Dreps, Erik English, Jieming Qi
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Patent number: 11662381Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.Type: GrantFiled: August 18, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Nathan Ross Blanchard, Venkat Harish Nammi, Dereje Yilma, Chad Andrew Marquart, Glen A. Wiedemeier, Jeffrey Kwabena Okyere, Erik English, Christopher Steffen, Vikram B Raj, Michael Wayne Harper
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Publication number: 20230055935Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.Type: ApplicationFiled: August 18, 2021Publication date: February 23, 2023Inventors: Nathan Ross Blanchard, VENKAT HARISH NAMMI, DEREJE YILMA, Chad Andrew Marquart, Glen A. Wiedemeier, JEFFREY KWABENA OKYERE, Erik English, Christopher Steffen, Vikram B. Raj, Michael Wayne Harper
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Patent number: 11528102Abstract: Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.Type: GrantFiled: August 18, 2021Date of Patent: December 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dereje Yilma, Nathan Ross Blanchard, Erik English, Chad Andrew Marquart, Glen A. Wiedemeier, Jeffrey Kwabena Okyere, James Crugnale, Christopher Steffen, Vikram B Raj, Michael Wayne Harper, Venkat Harish Nammi
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Patent number: 11322439Abstract: Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.Type: GrantFiled: November 13, 2019Date of Patent: May 3, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Erik English, Akil Khamisi Sutton, Pawel Owczarczyk
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Patent number: 11281249Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.Type: GrantFiled: September 23, 2019Date of Patent: March 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik English, Akil Khamisi Sutton, Pawel Owczarczyk, Michael Sperling
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Patent number: 11204635Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.Type: GrantFiled: September 23, 2019Date of Patent: December 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Pawel Owczarczyk, Akil Khamisi Sutton, Erik English
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Patent number: 11201767Abstract: Embodiments are directed to continuous time linear equalization including a low frequency equalization circuit which maintains DC gain. A first all-pass filter is coupled to an integrated filter, the integrated filter having a low-pass filter and a second all-pass filter. A high-pass filter is coupled to the first all-pass filter and the integrated filter, a differential input terminal being coupled to the first all-pass filter, the integrated filter, and the high-pass filter, where a differential output terminal is coupled to the high-pass filter.Type: GrantFiled: May 26, 2021Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik English, Chad Andrew Marquart, Pier Andrea Francese
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Patent number: 11152920Abstract: Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.Type: GrantFiled: September 23, 2019Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Patent number: 11119126Abstract: Techniques for a slope detector for voltage droop monitoring are described herein. An aspect includes receiving an input voltage by a circuit. Another aspect includes producing, by the circuit, a filtered offset voltage based on the input voltage. Another aspect includes determining whether the input voltage is lower than the filtered offset voltage. Yet another aspect includes, based on the input voltage being lower than the filtered offset voltage, indicating an imminent voltage droop condition in the input voltage.Type: GrantFiled: July 23, 2019Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik English, Michael Sperling
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Publication number: 20210143095Abstract: Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Inventors: Michael Sperling, Erik English, Akil Khamisi Sutton, Pawel Owczarczyk
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Publication number: 20210091753Abstract: Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Publication number: 20210089104Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Michael Sperling, Pawel Owczarczyk, Akil Khamisi Sutton, Erik English
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Publication number: 20210089071Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Erik English, Akil Khamisi Sutton, Pawel Owczarczyk, Michael Sperling
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Publication number: 20210025926Abstract: Techniques for a slope detector for voltage droop monitoring are described herein. An aspect includes receiving an input voltage by a circuit. Another aspect includes producing, by the circuit, a filtered offset voltage based on the input voltage. Another aspect includes determining whether the input voltage is lower than the filtered offset voltage. Yet another aspect includes, based on the input voltage being lower than the filtered offset voltage, indicating an imminent voltage droop condition in the input voltage.Type: ApplicationFiled: July 23, 2019Publication date: January 28, 2021Inventors: ERIK ENGLISH, MICHAEL SPERLING
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Patent number: 10833653Abstract: Aspects of the invention include a circuit including a power circuit having an amplifier, a resistor, a current source, and a first node, one end of the resistor being configured to couple to a power supply, the first node being coupled to an opposite end of the resistor, a first input terminal of the amplifier, and the current source. A voltage sensitive circuit includes a logic gate coupled to both a second input terminal of the amplifier and an output terminal of the amplifier at a second node.Type: GrantFiled: September 23, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English