Patents by Inventor Erik Ernst Hagersten

Erik Ernst Hagersten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11138121
    Abstract: A data management method for a processor to which a first cache, a second cache, and a behavior history table are allocated, includes tracking reuse information learning cache lines stored in at least one of the first cache and the second cache; recording the reuse information in the behavior history table; and determining a placement policy with respect to future operations that are to be performed on a plurality of cache lines stored in the first cache and the second cache, based on the reuse information in the behavior history table.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Erik Ernst Hagersten, Andreas Karl Sembrant, David Black-Schaffer
  • Patent number: 11023376
    Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, each node containing at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being private to at least one node from among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the first cache lines includes a first associated pointer pointing to a location of one of the second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Erik Ernst Hagersten
  • Patent number: 10915466
    Abstract: Caches may be vulnerable to side-channel attacks, such as Spectre and Meltdown, that involve speculative execution of instructions, revealing information about a cache that the attacker is not permitted to access. Access permission may be stored in the cache, such as in an entry of a cache table or in the region information for a cache table. Optionally, the access permission may be re-checked if the access permission changes while a memory instruction is pending. Optionally, a random index value may be stored in a cache and used, at least in part, to identify a memory location of a cacheline. Optionally, cachelines that are involved in speculative loads for memory instructions may be marked as speculative. On condition of resolving the speculative load as non-speculative, the cacheline may be marked as non-speculative; and on condition of resolving the speculative load as mis-speculated, the cacheline may be removed from the cache.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Erik Ernst Hagersten, David Black-Schaffer, Stefanos Kaxiras
  • Patent number: 10884925
    Abstract: A data management method for a computer system including at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, includes selecting a victim cache line to be evicted from the first cache; finding a VB location corresponding to the victim cache line from a set of the VB; copying data of the victim cache line to a data field of the VB location; copying a backward pointer (BP) associated with the victim cache line to a BP field of the VB location; and reclaiming victim space of the first cache using the VB.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Erik Ernst Hagersten, Andreas Karl Sembrant
  • Patent number: 10866891
    Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, wherein each node includes at least one processor, a first cache private to the node, a second cache at a higher level than the first cache, and a cache location buffer (CLB) private to the node, wherein, for at least one node of the plurality of nodes, at least one of the first cache and the second cache included in the at least one node includes at least one cache location that is capable of storing a compressed data unit of varying size, the CLB included in the at least one node is configured to store a plurality of CLB entries, each of the CLB entries including a plurality of location information values.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Erik Ernst Hagersten, Andreas Karl Sembrant, David Black-Schaffer
  • Publication number: 20190272239
    Abstract: Caches may be vulnerable to side-channel attacks, such as Spectre and Meltdown, that involve speculative execution of instructions, revealing information about a cache that the attacker is not permitted to access. Access permission may be stored in the cache, such as in an entry of a cache table or in the region information for a cache table. Optionally, the access permission may be re-checked if the access permission changes while a memory instruction is pending. Optionally, a random index value may be stored in a cache and used, at least in part, to identify a memory location of a cacheline. Optionally, cachelines that are involved in speculative loads for memory instructions may be marked as speculative. On condition of resolving the speculative load as non-speculative, the cacheline may be marked as non-speculative; and on condition of resolving the speculative load as mis-speculated, the cacheline may be removed from the cache.
    Type: Application
    Filed: February 27, 2019
    Publication date: September 5, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Erik Ernst HAGERSTEN, David Black-Schaffer, Stefanos Kaxiras
  • Publication number: 20190155732
    Abstract: A data management method for a computer system including at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, includes selecting a victim cache line to be evicted from the first cache; finding a VB location corresponding to the victim cache line from a set of the VB; copying data of the victim cache line to a data field of the VB location; copying a backward pointer (BP) associated with the victim cache line to a BP field of the VB location; and reclaiming victim space of the first cache using the VB.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Erik Ernst HAGERSTEN, Andreas Karl SEMBRANT
  • Publication number: 20190155731
    Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, wherein each node includes at least one processor, a first cache private to the node, a second cache at a higher level than the first cache, and a cache location buffer (CLB) private to the node, wherein, for at least one node of the plurality of nodes, at least one of the first cache and the second cache included in the at least one node includes at least one cache location that is capable of storing a compressed data unit of varying size, the CLB included in the at least one node is configured to store a plurality of CLB entries, each of the CLB entries including a plurality of location information values.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Erik Ernst Hagersten, Andreas Karl Sembrant, David Black-Schaffer
  • Publication number: 20190155733
    Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, each node containing at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being private to at least one node from among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the first cache lines includes a first associated pointer pointing to a location of one of the second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Erik Ernst Hagersten
  • Publication number: 20190155736
    Abstract: A data management method for a processor to which a first cache, a second cache, and a behavior history table are allocated, includes tracking reuse information learning cache lines stored in at least one of the first cache and the second cache; recording the reuse information in the behavior history table; and determining a placement policy with respect to future operations that are to be performed on a plurality of cache lines stored in the first cache and the second cache, based on the reuse information in the behavior history table.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Erik Ernst Hagersten, Andreas Karl Sembrant, David Black-Schaffer