Patents by Inventor Erik L. Welty

Erik L. Welty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for providing bus protocol simulation
    Patent number: 5708839
    Abstract: A method and apparatus for providing bus protocol simulation in a multi-processor data processing system (10). A plurality of edge interface circuits (14,16) are used to interface a first bus (32, 34, 36), which uses a first bus protocol, with a plurality of data processors (50-65), each of which uses a second bus protocol. A memory (90) within each edge interface circuit (14,16) is loaded with a plurality of values. Each of the plurality of values has a control portion and a data portion. The control portion of memory entry "N" is used to initiate the transfer of the data from memory entry "N+1". In an alternate embodiment, multi-processor data processing system (210) includes a plurality of data processors (250-258) and a plurality of edge interface circuits (214-217).
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: January 13, 1998
    Assignee: Motorola, Inc.
    Inventors: Michael F. Wiles, Michael G. Gallup, Erik L. Welty
  • Method for complex data movement in a multi-processor data processing system
    Patent number: 5603046
    Abstract: A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: February 11, 1997
    Assignee: Motorola Inc.
    Inventors: Michael F. Wiles, Meltin Bell, Michael G. Gallup, L. Rodney Goke, Jack R. Davis, Erik L. Welty
  • Multi-processor data processing system having multiple ports coupled to multiple interface circuits
    Patent number: 5548771
    Abstract: A multi-processor data processing system (10) includes an array (12) of one or more data processors (50-65). Data processing system (10) has edge interface circuits (14,16) for transferring control and data to and from the array (12). A data bus (32), an address bus (34), and a control bus (36) each transfers information to and from the array (12), the edge interfaces (14,16), and a bus interface controller (22). In an alternate embodiment, multi-processor data processing system (210) includes an array (212) of one or more data processors (250-258). Data processing system (210) has edge interfaces (214-217) for transferring control and data to and from the array (212). A data bus (232), an address bus (234), and a control bus (236) each transfers information to and from the array (212), the edge interfaces (214-217), and a bus interface controller (222).
    Type: Grant
    Filed: November 2, 1993
    Date of Patent: August 20, 1996
    Assignee: Motorola Inc.
    Inventors: Jack R. Davis, Michael G. Gallup, L. Rodney Goke, Erik L. Welty, Michael F. Wiles