Patents by Inventor Erik M. Schlanger
Erik M. Schlanger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111441Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: ApplicationFiled: November 29, 2023Publication date: April 4, 2024Inventors: Rishabh Jain, Erik M. Schlanger
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Patent number: 11868628Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: GrantFiled: May 13, 2022Date of Patent: January 9, 2024Assignee: Oracle International CorporationInventors: Rishabh Jain, Erik M. Schlanger
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Publication number: 20220276794Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: ApplicationFiled: May 13, 2022Publication date: September 1, 2022Inventors: Rishabh Jain, Erik M. Schlanger
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Patent number: 11334262Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: GrantFiled: July 31, 2020Date of Patent: May 17, 2022Assignee: Oracle International CorporationInventors: Rishabh Jain, Erik M. Schlanger
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Publication number: 20200363967Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Rishabh Jain, Erik M. Schlanger
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Patent number: 10732865Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: GrantFiled: September 23, 2015Date of Patent: August 4, 2020Assignee: Oracle International CorporationInventors: Rishabh Jain, Erik M. Schlanger
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Patent number: 10725947Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.Type: GrantFiled: November 29, 2016Date of Patent: July 28, 2020Assignee: Oracle International CorporationInventors: Rishabh Jain, David A. Brown, Michael Duller, Christopher Joseph Daniels, Erik M. Schlanger
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Publication number: 20180150259Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: RISHABH JAIN, DAVID A. BROWN, MICHAEL DULLER, CHRISTOPHER JOSEPH DANIELS, ERIK M. SCHLANGER
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Publication number: 20170083257Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Rishabh Jain, Erik M. Schlanger
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Publication number: 20130070849Abstract: A method and device that allow picture slices of a Video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.Type: ApplicationFiled: September 14, 2012Publication date: March 21, 2013Applicant: NetLogic Microsystems, Inc.Inventors: Erik M. SCHLANGER, Brendan D. Donahe, Eric Swartzendruber, Eric J. DeVolder
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Patent number: 8331446Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.Type: GrantFiled: August 31, 2008Date of Patent: December 11, 2012Assignee: NetLogic Microsystems, Inc.Inventors: Erik M. Schlanger, Brendan D. Donahe, Eric Swartzendruber, Eric J. DeVolder
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Publication number: 20100111166Abstract: A device is disclosed having a motion vector processing module to determine a first set of motion vectors associated with a macroblock of a video picture. A motion vector reduction module determines a second set of motion vectors, based on the first set of motion vectors, associated the macroblock, the second set having fewer motion vectors than the first set.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: RMI CORPORATIONInventors: Erik M. Schlanger, Brendan D. Donahe, Eric Swartzendruber, Sandip J. Ladhani
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Publication number: 20100053181Abstract: A memory controller is disclosed that allocates local memory space to a set of macroblocks of a picture being processed. Information associated with a specific macroblock of the set of macroblocks is written to non-local memory when it is no longer needed to complete processing of a current row of macroblocks. When information associated with the specific macroblock is later needed to process a different row of macroblocks, the memory controller allocates local memory space to the specific macroblock and stores the previously saved information from non-local memory to the local memory.Type: ApplicationFiled: August 31, 2008Publication date: March 4, 2010Applicant: RAZA MICROELECTRONICS, INC.Inventors: Erik M. Schlanger, Brendan D. Donahe
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Publication number: 20100054339Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.Type: ApplicationFiled: August 31, 2008Publication date: March 4, 2010Applicant: RAZA MICROELECTRONICS, INC.Inventors: Erik M. Schlanger, Brendan D. Donahe, Eric Swartzendruber, Eric J. DeVolder