Patents by Inventor Erik Newton

Erik Newton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11868774
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Publication number: 20210406020
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 11138012
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Publication number: 20200293320
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 17, 2020
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 10613864
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Publication number: 20190286448
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 7106705
    Abstract: For a communication system (e.g. UMTS with CDMA radio interface), the invention draws a distinction between services with high and low data rate dynamics and uses a matched type of signaling for the transport formats currently being used. The data rate of the data for a service can fluctuate greatly and/or rapidly over time (high dynamics), or may fluctuate only a little and/or slowly (low dynamics). The data for the services are transmitted via a common physical channel, with in-band signaling being used for signaling the transport format for the services with high data rate dynamics, and with signaling in a separate channel being used for the services with low data rate dynamics.
    Type: Grant
    Filed: November 25, 1999
    Date of Patent: September 12, 2006
    Assignee: Siemens AG
    Inventors: Christoph Mecklenbräuker, Michael Benz, Anja Klein, Reinhard Köhn, Jörn Krause, Christian Menzel, Enric Mitjana, Erik Newton, Martin Öttl, Dave Randall, Armin Sitte, Jean-Michel Traynard, Thomas Ulrich