Abstract: A data processing apparatus is provided, comprising plural processing units configured to execute plural processes, a storage unit configured to store data required for the plural processes; and a protection unit configured to control access by the plural processes to the storage unit. The protection unit is configured to define an allocated access region of the storage unit for each process of the plural processes, wherein the protection unit is configured to deny access for each the process outside the allocated access region and wherein allocated access regions are defined to be non-overlapping. The protection unit is configured to define each allocated access region as a contiguous portion of the storage unit between a lower region limit and an upper region limit, and the protection unit is configured such that when the lower region limit is modified the lower region limit cannot be decreased and such that when the upper region limit is modified the upper region limit cannot be decreased.

Abstract: The present invention provides filter circuitry for reducing noise in an input stream of image signals having luminance and chrominance components. Spatial filter circuitry is provided which, for a current image signal of the input stream, generates a spatially filtered internal signal from at least the luminance component of the current image signal. Comparison circuitry is configured to compare the current image signal with temporal data derived from multiple image signals of the input stream, and to generate a control signal dependent on the comparison. Combining circuitry is then used to combine, in a ratio determined by the control signal, the spatially filtered internal signal with at least a luminance component derived from the temporal data, in order to generate at least the luminance component of a current output image signal that forms a noise reduced version of the current image signal.

Abstract: A VOC free cross linking product for waterborn coatings is described. The crosslinking product comprises at least one cross linking agent and at least one viscosity reducing compound.

Abstract: A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes.

Abstract: A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.

Abstract: A data processing apparatus is configured to perform secure data processing operations and non-secure data processing operations, wherein the apparatus includes a master device with a secure domain and a non-secure domain. Components of the master device operate in the secure domain when performing secure data processing operations and operate in the non-secure domain when performing the non-secure data processing operations. A slave device is configured to perform a delegated data processing operation specified by the master device and a communication bus connecting the master device to the slave device. The delegated operation is initiated by an issuing component in the master device, wherein the slave device includes a security inheritance mechanism configured to cause the delegated operation to inherit a non-secure security status or a secure status depending upon whether the issuing component in the master device is operating in the non-secure domain or the secure domain.

Abstract: A video processing apparatus and method are provided, the video processing apparatus comprising first stage video processing circuitry and second stage video processing circuitry. The first stage video processing circuitry receives input video data and performs one or more processing operations on the input video data to generate an intermediate representation of the input video data. The intermediate representation comprises first and second separate data portions, with the first data portion containing transient data derived from the input video data and the second data portion containing long term data derived from the input video data. Transient data is only required for processing of a single video frame, while the long term data is required for processing of at least two video frames.

Abstract: A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.

Abstract: A data processing apparatus includes a vector register bank having a plurality of vector registers, each register including a plurality of storage cells, each cell storing a data element. A vector processing unit is provided for executing a sequence of vector instructions. The processing unit is arranged to issue a set rearrangement enable signal to the vector register bank. The write interface of the vector register bank is modified to provide not only a first input for receiving the data elements generated by the vector processing unit during normal execution, but also has a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of the predetermined rearrangement operation.

Abstract: A method for treating a wooden, bamboo and/or cork floor treated with at least one maintenance material and a treated wooden, bamboo and/or cork floor obtained by the method. The method comprises applying a stripping formula on the wooden, bamboo and/or cork floor; allowing the stripping formula to interact with the at least one maintenance material; applying mechanical treatment to release the at least one maintenance material; and removing the at least one maintenance material and the stripping formula.

Abstract: The present invention provides filter circuitry for reducing noise in an input stream of image signals having luminance and chrominance components. Spatial filter circuitry is provided which, for a current image signal of the input stream, generates a spatially filtered internal signal from at least the luminance component of the current image signal. Comparison circuitry is configured to compare the current image signal with temporal data derived from multiple image signals of the input stream, and to generate a control signal dependent on the comparison. Combining circuitry is then used to combine, in a ratio determined by the control signal, the spatially filtered internal signal with at least a luminance component derived from the temporal data, in order to generate at least the luminance component of a current output image signal that forms a noise reduced version of the current image signal.

Abstract: The invention relates to an arrangement (1) for conveying of sheets (2a, b), comprising upper and lower receiving rolls (3, 4), an upper belt element (5) and a receiving surface (6). The belt element (5) extends in a region above the receiving surface (6). The sheets (2a, b) are conveyed in a substantially horizontal direction of movement (7) towards the receiving rolls (3, 4), which receiving rolls (3, 4) during rotation move the sheets (2a, b) one after another between and past the receiving rolls (3, 4), during which the respective sheet (2a, b), after passing between and past the receiving rolls (3, 4), are situated between said receiving surface (6) and upper belt element (5). The sheets (2a, b) between the upper belt element (5) and the receiving surface (6) are placed on one another such that a rear edge (8) of a sheet (2a) passing through and between the receiving rolls (3, 4) is overlapped by a front edge (9) of a following sheet (2b).

Abstract: A method for coating a floor, wherein said method comprises applying an aqueous dispersion comprising polyurethane, an acrylate or a hybride or mixture thereof; drying said coating and subjecting the physically dry coating to ultraviolet radiation whereby a cured coating is obtained. Also claimed is reactive additives suitable for use in the methods as well as the floor itself.

Abstract: A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.

Abstract: A video encoding apparatus for encoding a video stream comprising: a reference frame cache configured to cache reference frame video data retrieved from a reference frame storage unit in external memory, the reference frame video data cached in the reference frame cache being derived from an individual frame of the video stream; a first source frame storage unit configured to store a first block of unencoded video data taken from a first source frame of the video stream; a second source frame storage unit configured to store a second block of unencoded video data taken from a second source frame of the video stream; a first video encoder configured to perform a first encoding operation to encode the first block of unencoded video data with reference to the reference frame video data cached in the reference frame cache; and a second video encoder configured to perform a second encoding operation to encode said second block of unencoded video data with reference to the reference frame video data cached in the r

Abstract: A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Abstract: A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.

Abstract: A video processing apparatus and method are provided, the video processing apparatus comprising first stage video processing circuitry and second stage video processing circuitry. The first stage video processing circuitry receives input video data and performs one or more processing operations on the input video data to generate an intermediate representation of the input video data. The intermediate representation comprises first and second separate data portions, with the first data portion containing transient data derived from the input video data and the second data portion containing long term data derived from the input video data. Transient data is only required for processing of a single video frame, whilst the long term data is required for processing of at least two video frames.

Abstract: A data processing apparatus and method are provided for performing a predetermined rearrangement operation. The data processing apparatus comprises a vector register bank having a plurality of vector registers, with each vector register comprising a plurality of storage cells such that the plurality of vector registers provide a matrix of storage cells. Each storage cell is arranged to store a data element. A vector processing unit is provided for executing a sequence of vector instructions in order to apply operations to the data elements held in the vector register bank. Responsive to a vector matrix rearrangement instruction specifying a predetermined rearrangement operation to be performed on the data elements in the matrix of storage cells, the vector processing unit is arranged to issue a set rearrangement enable signal to the vector register bank.

Abstract: A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes.