Patents by Inventor Erik S. Panu

Erik S. Panu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VIP assisted method and apparatus to enable SOC integration and software development
    Patent number: 9710581
    Abstract: Using verification IP (VIP), the related design IP (DIP) can be integrated into a system on a chip (SOC) without requiring the IP component. Using a normalized framework, a software module can be integrated into the VIP software stack enabling the customized management of the VIP beyond the standard specification defined behaviors. Then, the modified software stack can be used to manage both behaviors defined by the specification and the design specific behaviors. The VIP can then be used in place of the DIP for SOC development.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 18, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu
  • Enabling IP execution on a simulation execution platform
    Patent number: 9208282
    Abstract: In a system and method that simulates a design including a third party IP component, a driver for the IP component is compiled and executed in a workstation implementing the simulation platform for the design. The source code for the driver is modified to allow the simulation to reroute certain functions that would cause the simulator to hang until an event occurs that would unlock the simulation. The rerouting includes storing instruction location, state information, and any other context information needed to restore a paused function. The saved information is stored in a stack that is traversed upon detection of the event.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 8, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu, Sandeep Suresh Pendharkar
  • Formalizing IP driver interface
    Patent number: 9183331
    Abstract: A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu, Levent Caglar