Patents by Inventor Erin Catherine Jones

Erin Catherine Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7960790
    Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanararyan G. Hegde, Meikei Ieong, Erin Catherine Jones
  • Patent number: 7453123
    Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, Meikei Ieong, Erin Catherine Jones
  • Publication number: 20080246090
    Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
    Type: Application
    Filed: May 13, 2008
    Publication date: October 9, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, MeiKei Ieong, Erin Catherine Jones
  • Patent number: 7205185
    Abstract: A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: April 17, 2007
    Assignee: International Busniess Machines Corporation
    Inventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, MeiKei Ieong, Erin Catherine Jones
  • Publication number: 20020197836
    Abstract: A method for forming variable oxide thicknesses across semiconductor chips comprises providing a silicon semiconductor substrate having pre-selected areas open to silicon surface using a photoresist layer; immersing the silicon semiconductor substrate in an HF type electrolytic bath to produce a porous silicon area; and removing the photoresist layer and oxidizing the silicon semiconductor substrate to produce a plurality of thicknesses of gate oxide on the silicon semiconductor substrate.
    Type: Application
    Filed: June 11, 2001
    Publication date: December 26, 2002
    Applicant: International Business Machines Corporation
    Inventors: S. Sundar Kumar Iyer, Suryanarayan G. Hegde, Erin Catherine Jones, Harald F. Okorn-Schmidt
  • Patent number: 6281551
    Abstract: A back-plane for a semiconductor device, includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: August 28, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kevin Kok Chan, Christopher Peter D'Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari
  • Patent number: 6057212
    Abstract: A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafers to form a bond between the first and second wafers, and detaching a portion of the first wafer from the second wafer. Thus, a device, such as a back-plane for a semiconductor device, formed by the method includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: Kevin Kok Chan, Christopher Peter D'Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari