Patents by Inventor Erminio Di Martino
Erminio Di Martino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983073Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.Type: GrantFiled: July 27, 2022Date of Patent: May 14, 2024Assignee: Micron Technology, Inc.Inventors: Luca Porzio, Ferdinando Pascale, Roberto Izzi, Marco Onorato, Erminio Di Martino
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Publication number: 20240036977Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Luca Porzio, Ferdinando Pascale, Roberto Izzi, Marco Onorato, Erminio Di Martino
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Patent number: 11573702Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.Type: GrantFiled: May 26, 2021Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
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Patent number: 11347402Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.Type: GrantFiled: July 26, 2019Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Domenico Monteleone, Giacomo Bernardi, Luca Porzio, Graziano Mirichigni, Stefano Zanardi, Erminio Di Martino
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Patent number: 11309055Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.Type: GrantFiled: December 20, 2018Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Claudio Giaccio, Ferdinando Pascale, Raffaele Mastrangelo, Erminio Di Martino, Ferdinando D'Alessandro, Cristiano Castellano, Andrea Castaldo
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Patent number: 11282553Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: GrantFiled: December 31, 2019Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Publication number: 20210341963Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Publication number: 20210286516Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.Type: ApplicationFiled: May 26, 2021Publication date: September 16, 2021Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
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Patent number: 11061431Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: GrantFiled: June 28, 2018Date of Patent: July 13, 2021Assignee: Micron Technology, Inc.Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Patent number: 11042301Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.Type: GrantFiled: December 13, 2018Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
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Patent number: 10860482Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: GrantFiled: February 11, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Publication number: 20200202971Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Claudio Giaccio, Ferdinando Pascale, Raffaele Mastrangelo, Erminio Di Martino, Ferdinando D'Alessandro, Cristiano Castellano, Andrea Castaldo
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Publication number: 20200192570Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
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Publication number: 20200152245Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: ApplicationFiled: December 31, 2019Publication date: May 14, 2020Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Patent number: 10546620Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: GrantFiled: June 28, 2018Date of Patent: January 28, 2020Assignee: Micron Technology, Inc.Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Publication number: 20200004289Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Publication number: 20200005840Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Claudio Giaccio, Ferdinando Pascale, Erminio Di Martino, Raffaele Mastrangelo, Ferdinando D'Alessandro, Andrea Castaldo, Cristiano Castellano
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Publication number: 20190347012Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Domenico Monteleone, Giacomo Bernardi, Luca Porzio, Graziano Mirichigni, Stefano Zanardi, Erminio Di Martino
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Patent number: 10365835Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.Type: GrantFiled: May 28, 2014Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventors: Domenico Monteleone, Giacomo Bernardi, Luca Porzio, Graziano Mirichigni, Stefano Zanardi, Erminio Di Martino
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Publication number: 20190171567Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus mau include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth