Abstract: Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter.

Abstract: A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.

Abstract: A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.

Abstract: A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.

Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) driver circuit that provides a DC test signal for testing a semiconductor device, and a feedback circuit that senses the DC test signal at an output of the PMU driver circuit and sends the sensed DC test signal to an input of the PMU driver circuit for compensating the DC test signal.

Abstract: Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter.

Abstract: A semiconductor structure for controlling the temperature of a component is described. The structure includes a resistive layer having one or more channels provided therein and having a resistance characteristic such that a signal applied thereto causes the resistive layer to generate heat. A cooling fluid is fed through the one or more channels to cool both the structure and a component disposed on the structure. By providing the cooling channels in the resistive layer, the heating and cooling sources are intermingled. The structure can optionally include precising and vacuum clamping structures, to locate and hold the component that is to be temperature controlled.

Abstract: Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits, digital sigma delta modulator circuitry used to generate digital bit streams representative of analog reference levels, and programmable digital signal processing circuitry. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit; and, the digital signal processing circuitry is used to monitor and control levels produced by the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

Abstract: Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits and sigma delta modulator circuitry, which is used to generate digital bit streams representative of analog reference levels. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

Abstract: A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switch is used to change from the parallel test mode to the scan test mode. A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode. The speed of the scan test mode is increased by interleaving the memory and reading test vectors out of the memory in parallel. Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT). Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.

Abstract: Automatic test equipment utilizing a pipelined sequencer to retrieve test vectors from a random access memory during execution of a test pattern. The order of execution of the test vectors need not be sequential and can be dynamically altered by conditions measured during execution of a test pattern. Though pipelined, the sequencer provides one vector per cycle, even if the execution order is dynamically altered. The sequencer, because it is pipelined, can be implemented with relatively low cost, though slower speed, components. The disclosed sequencer is implemented with CMOS components.

Abstract: Apparatus for providing high speed control of digital test patterns and analog instruments in automatic circuit testing apparatus including a sequence controller including a random access memory ("RAM") for microcode and an address generator for selectively addressing instructions in said random access memory, a sequence address bus connected to the address generator of the sequence controller, digital test pattern RAM connected to the sequence address bus, and analog instruments including associated RAM loaded with microcode for the instruments and connected to the sequence address bus.