Patents by Inventor Esfir Natanzon
Esfir Natanzon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134443Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.Type: ApplicationFiled: October 19, 2023Publication date: April 25, 2024Inventors: Efraim ROTEM, Eliezer WEISSMANN, Doron RAJWAN, Yoni AIZIK, Esfir NATANZON, Nir ROSENZWEIG, Nadav SHULMAN, Bart PLACKLE
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Publication number: 20230418361Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11815979Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.Type: GrantFiled: August 22, 2017Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Yoni Aizik, Esfir Natanzon, Nir Rosenzweig, Nadav Shulman, Bart Plackle
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Patent number: 11789516Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: GrantFiled: May 22, 2020Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Publication number: 20220179473Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: ApplicationFiled: May 22, 2020Publication date: June 9, 2022Applicant: Intel CorporationInventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11216276Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.Type: GrantFiled: December 27, 2018Date of Patent: January 4, 2022Assignee: Intel CorporationInventors: Eliezer Weissmann, Hisham Abu-Salah, Daniel Lederman, Nir Rosenzweig, Efraim Rotem, Esfir Natanzon, Yevgeni Sabin, Shay Levy
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Patent number: 11188138Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.Type: GrantFiled: November 30, 2018Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Michael Bitan, Andrey Gabdulin, Efraim Rotem, Eli Efron, Nadav Shulman, David Ben Shimon, Nir Levitin, Esfir Natanzon
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Publication number: 20210191494Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.Type: ApplicationFiled: August 22, 2017Publication date: June 24, 2021Inventors: Efraim ROTEM, Eliezer WEISSMANN, Doron RAJWAN, Yoni AIZIK, Esfir NATANZON, Nir ROSENZWEIG, Nadav SHULMAN, Bart PLACKLE
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Patent number: 11029744Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.Type: GrantFiled: December 29, 2017Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira, Lily P. Looi, Bart Plackle, Nadav Shulman
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Publication number: 20200210184Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Eliezer Weissmann, Hisham Abu-Salah, Daniel Lederman, Nir Rosenzweig, Efraim Rotem, Esfir Natanzon, Yevgeni Sabin, Shay Levy
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Publication number: 20200174541Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Michael Bitan, Andrey Gabdulin, Efraim Rotem, Eli Efron, Nadav Shulman, David Ben Shimon, Nir Levitin, Esfir Natanzon
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Patent number: 10620682Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.Type: GrantFiled: December 21, 2017Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Nikhil Gupta, Israel Hirsh, Esfir Natanzon, Nir Rosenzweig, Efraim Rotem, Guy M. Therien, Ankush Varma, Eliezer Weissmann
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Patent number: 10345889Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: GrantFiled: August 4, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20190204893Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira, Lily P. Looi, Bart Plackle, Nadav Shulman
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Publication number: 20190196573Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Nikhil Gupta, Israel Hirsh, Esfir Natanzon, Nir Rosenzweig, Efraim Rotem, Guy M. Therien, Ankush Varma, Eliezer Weissmann
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Patent number: 10289514Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.Type: GrantFiled: June 30, 2014Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
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Patent number: 10095302Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.Type: GrantFiled: August 29, 2016Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: Ariel Gur, Daniel J Ragland, Ofer Nathan, Nadav Shulman, Esfir Natanzon
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Publication number: 20180120924Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: ApplicationFiled: August 4, 2017Publication date: May 3, 2018Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20180059763Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.Type: ApplicationFiled: August 29, 2016Publication date: March 1, 2018Inventors: Ariel Gur, Daniel J Ragland, Ofer Nathan, Nadav Shulman, Esfir Natanzon
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Patent number: 9904339Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.Type: GrantFiled: September 10, 2014Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Dorit Shapira, Efraim Rotem, Doron Rajwan, Nadav Shulman, Esfir Natanzon, Nir Rosenzweig