Abstract: An exhaust gas heat exchanger having stacked flat tubes includes a stacked tube body configured by stacking a plurality of flat tubes in multiple tiers with spaces therebetween and arranged inside a case; exhaust gas flows in from a first end part of the stacked tube body in a tube axis direction, circulates through each flat tube, and flows out from the a second end part; and cooling water from the case is supplied to the first end part to circulate along an exterior surface side of each flat tube. The cooling water is introduced into the tubes from two locations of the case and in mutually opposite directions which are parallel to flat surfaces of the tubes and vertical in the axis direction of the flat tubes.

Abstract: An object of the present invention is to realize a display device having a layered wiring structure, that is capable of detecting leakage without fail by using a simple testing circuit. Source bus lines (SL) are wired such that, in the layered region, two source bus lines (SL) adjacent in a vertical direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column, and two source bus lines (SL) adjacent in a horizontal direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column. Potentials of different magnitudes are supplied respectively to source bus lines (SL) of odd-numbered columns and source bus lines (SL) of even-numbered columns via testing lines.

Abstract: In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines, the plurality of source bus lines are wired to the plurality of layers such that taking source bus lines of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines to which positive video signals are applied matches the number of source bus lines to which negative video signals are applied in each of the layers in each of horizontal scanning periods.

Abstract: An exhaust gas heat exchanger having stacked flat tubes includes a stacked tube body configured by stacking a plurality of flat tubes in multiple tiers with spaces therebetween and arranged inside a case; exhaust gas flows in from a first end part of the stacked tube body in a tube axis direction, circulates through each flat tube, and flows out from the a second end part; and cooling water from the case is supplied to the first end part to circulate along an exterior surface side of each flat tube. The cooling water is introduced into the tubes from two locations of the case and in mutually opposite directions which are parallel to flat surfaces of the tubes and vertical in the axis direction of the flat tubes.

Abstract: An object of the present invention is to suppress deterioration of display quality due to difference in wiring resistance and capacitance between the layers in a display device having a layered wiring structure. In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines (SL), the plurality of source bus lines SL are wired to the plurality of layers such that taking source bus lines (SL) of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines (SL) to which positive video signals are applied matches the number of source bus lines (SL) to which negative video signals are applied in each of the layers in each of horizontal scanning periods.

Abstract: An object of the present invention is to realize a display device having a layered wiring structure, that is capable of detecting leakage without fail by using a simple testing circuit. Source bus lines (SL) are wired such that, in the layered region, two source bus lines (SL) adjacent in a vertical direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column, and two source bus lines (SL) adjacent in a horizontal direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column. Potentials of different magnitudes are supplied respectively to source bus lines (SL) of odd-numbered columns and source bus lines (SL) of even-numbered columns via testing lines.

Abstract: A display device is provided which is capable of preventing a malfunction and carrying out a common reverse drive without increasing electric power consumption. The display driver (a) supplies a voltage of a common electrode, whose a polarity is determined in accordance with (i) an oscillation circuit output signal (OCOUT) which is transmitted via a first wire different from a second wire used during a serial transmission and (ii) a SCS signal and (b) controls a reverse timing of the polarity of the voltage of the common electrode in accordance with the oscillation circuit output signal (OCOUT) and the SCS signal.

Abstract: A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T9) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T1) which supplies the ON voltage to a control terminal of the transistor (T2) in accordance with an input signal (IN); a transistor (T4) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T2). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.

Abstract: A display device employing CC driving switches from (i) a first mode in which to carry out a display by converting resolution of a video signal by a factor of 2 in a column-wise direction to (ii) a second mode in which to carry out a display at the resolution of the video signal. During the first mode, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent scanning signal lines and that are adjacent to each other in the column-wise direction, and a direction of change in the signal potentials written to the pixel electrodes varies every two adjacent rows (2-line inversion driving). During the second mode, the direction of change in the signal potentials written to the pixel electrodes lines varies every single row (1-line inversion driving).

Abstract: A semiconductor device (10) provided with at least a plurality of transistors and bootstrap capacitors (Ca1 and Cb1), the semiconductor device (10) includes: a semiconductor layer (22) made of the same material as a channel layer of each of the transistors; a capacitor electrode (24) formed in an upper layer of the semiconductor layer (22); and a clock signal line (17) formed in an upper layer of the capacitor electrode (24), the capacitor electrode (24) being connected to a gate electrode of each of the transistors, the clock signal line (17) being supplied with a clock signal (CK) from outside the semiconductor device (10), the capacitors (Ca1 and Cb1) each being formed in an overlap section where the semiconductor layer (22), the gate insulating film (23) and the capacitor electrode (24) overlap one another, the overlap section and the clock signal line (17) overlapping each other when viewed from above.

Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: An embodiment of the present invention switches, in a display driving circuit of a liquid crystal display device which carries out CC driving, between a two-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every two horizontal scanning periods and a one-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every one horizontal scanning period. In at least one example embodiment, a polarity signal reverses its polarity every two horizontal scanning periods in the two-line reversal driving mode, and reverses its polarity every one horizontal scanning period in the one-line reversal driving mode.

Abstract: A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.

Abstract: A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initializat

Abstract: In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.

Abstract: A display device is provided which is capable of preventing a malfunction and carrying out a common reverse drive without increasing electric power consumption. The display driver (a) supplies a voltage of a common electrode, whose a polarity is determined in accordance with (i) an oscillation circuit output signal (OCOUT) which is transmitted via a first wire different from a second wire used during a serial transmission and (ii) a SCS signal and (b) controls a reverse timing of the polarity of the voltage of the common electrode in accordance with the oscillation circuit output signal (OCOUT) and the SCS signal.

Abstract: In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.

Abstract: A display driving circuit which carries out CC driving is configured such that a polarity of a data signal to be supplied to a source line is reversed every two horizontal scanning periods and a signal electric potential written from the source line to a pixel electrode changes in a different direction every two adjacent rows. In at least one example embodiment, this allows, in a display device which carries out CC driving, enhancement of a display quality by removing lateral stripes that are produced in a display video while n-line reversal driving is being carried out.