Patents by Inventor Ettore Amirante
Ettore Amirante has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240153551Abstract: Various implementations described herein are related to a device having multi-page memory with a first core array and bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines. The device may have wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines. The device may have buried metal lines formed within a substrate, and the buried metal lines may be used to couple the wordline drivers to the first wordlines.Type: ApplicationFiled: November 3, 2022Publication date: May 9, 2024Inventors: Andy Wangkun Chen, Vivek Asthana, Sony, Ettore Amirante, Yew Keong Chong
-
Publication number: 20230411351Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.Type: ApplicationFiled: May 24, 2022Publication date: December 21, 2023Inventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan, Vivek Asthana, Ettore Amirante
-
Patent number: 11837543Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.Type: GrantFiled: August 28, 2020Date of Patent: December 5, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Patent number: 11475200Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.Type: GrantFiled: June 4, 2020Date of Patent: October 18, 2022Assignee: Arm LimitedInventors: Yulin Shi, Vincent Philippe Schuppe, Ettore Amirante
-
Publication number: 20220293522Abstract: Various implementations described herein are directed to a method for routing buried power rails underneath a memory instance. The method may identify first rails of the buried power rails disposed in a first layer and second rails of the buried power rails disposed perpendicular to the first rails in a second layer. The method may identify long rails of the first rails with a first length and short rails of the first rails with a second length that is less than the first length. The method may separately couple the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Sriram Thyagarajan, Ettore Amirante, Andy Wangkun Chen, Yew Keong Chong, Sony .
-
Patent number: 11443777Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.Type: GrantFiled: September 11, 2020Date of Patent: September 13, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Patent number: 11380384Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.Type: GrantFiled: August 28, 2020Date of Patent: July 5, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Patent number: 11328750Abstract: Various implementations described herein are related to a device with a backside power network. The backside power network may have a buried power rail that is coupled to ground. The device may have a read-only memory (ROM) cell that is coupled between at least one bitline and the buried power rail, and the ROM cell may be coupled to ground by way of the buried power rail.Type: GrantFiled: January 22, 2021Date of Patent: May 10, 2022Assignee: Arm LimitedInventors: Ettore Amirante, Andy Wangkun Chen, Yew Keong Chong, Sony
-
Publication number: 20220084561Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.Type: ApplicationFiled: September 11, 2020Publication date: March 17, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony N/A, Ettore Amirante, Ayush Kulshrestha
-
Publication number: 20220077857Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Patent number: 11271567Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.Type: GrantFiled: September 4, 2020Date of Patent: March 8, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Publication number: 20220068813Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Publication number: 20220068346Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
-
Publication number: 20210383050Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Inventors: Yulin Shi, Vincent Philippe Schuppe, Ettore Amirante
-
Patent number: 11170843Abstract: Various implementations described herein are related to a device having a bitcell. The device may include horizontal bitlines coupled to the bitcell. The horizontal bitlines may include multiple first read bitlines disposed in a horizontal direction with respect to the bitcell. The device may include vertical bitlines coupled to the bitcell. The vertical bitlines may include multiple second read bitlines disposed in a vertical direction with respect to the bitcell.Type: GrantFiled: March 19, 2020Date of Patent: November 9, 2021Assignee: Arm LimitedInventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan, Ettore Amirante
-
Publication number: 20210295898Abstract: Various implementations described herein are related to a device having a bitcell. The device may include horizontal bitlines coupled to the bitcell. The horizontal bitlines may include multiple first read bitlines disposed in a horizontal direction with respect to the bitcell. The device may include vertical bitlines coupled to the bitcell. The vertical bitlines may include multiple second read bitlines disposed in a vertical direction with respect to the bitcell.Type: ApplicationFiled: March 19, 2020Publication date: September 23, 2021Inventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan, Ettore Amirante
-
Patent number: 11068639Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.Type: GrantFiled: October 19, 2018Date of Patent: July 20, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong
-
Publication number: 20200125693Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Marlin Wayne Frederick, Jr., Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong
-
Patent number: 7995366Abstract: A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column.Type: GrantFiled: August 31, 2009Date of Patent: August 9, 2011Assignee: Infineon Technologies AGInventors: Martin Ostermayr, Ettore Amirante, Peter Huber
-
Publication number: 20110049576Abstract: A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column.Type: ApplicationFiled: August 31, 2009Publication date: March 3, 2011Inventors: Martin Ostermayr, Ettore Amirante, Peter Huber