Abstract: A variable configuration accounting machine having a central processor unit (CPU) of an LSI (Large Scale Integration) microprocessor type and a plurality of peripheral units selectively connectable to the CPU which gives a selected configuration to the machine. The CPU is connected to a pair of memories. The first memory stores instructions and data, and the second memory stores microprograms. The capacity of both memories is variable according to the number and type of the peripheral units connected to the CPU for a given configuration of the machine. In the second memory is permanently stored an initialization microprogram that, when activated by the operator, automatically causes the identification by the CPU of the number and type of peripheral units connected to the CPU.

Abstract: There is disclosed an accounting system comprising a computer, an insertion device for receiving and printing on a card and including means for writing information on and reading information from a magnetic track on the card. A control unit operates in conjunction with the computer to control feed of the card in the insertion device and the said writing and reading operations, and to detect the occurrence of errors in the reading or writing. A register is arranged to count the number of times that a reading or writing operation has been performed. When an error is detected the computer repeats the operation until either the operation is performed without an error being detected or the register indicates that the operation has been repeated a predetemined number of times.

Abstract: A multiple control unit for selectively connecting a plurality of peripheral units to a central processor comprising a register for storing the interruptions coming from the peripherals; a disabling circuit for disabling the cell storing the interruption executed by the central processor in response to an end-of processing signal generated from the CPU.

Abstract: An information recording system comprises a peripheral control unit for recording bits of a character one at a time coincident with the middle of a record time interval. The peripheral control unit is responsive to a central unit which cyclically transmits microinstructions to the peripheral control unit coincidentally with transfer of bits to said record device from a register storing the bits of a character to be recorded.