Abstract: Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

Abstract: A stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters.

Abstract: A stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters.

Abstract: A method for implementing a stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters.

Abstract: A method for implementing a stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters.

Abstract: A method, apparatus, and computer program product for scheduling stream-based applications in a distributed computer system with configurable networks are provided. The method includes choosing, at a highest temporal level, jobs that will run, an optimal template alternative for the jobs that will run, network topology, and candidate processing nodes for processing elements of the optimal template alternative for each running job to maximize importance of work performed by the system. The method further includes making, at a medium temporal level, fractional allocations and re-allocations of the candidate processing elements to the processing nodes in the system to react to changing importance of the work. The method also includes revising, at a lowest temporal level, the fractional allocations and re-allocations on a continual basis to react to burstiness of the work, and to differences between projected and real progress of the work.

Abstract: A method, system, and computer program product for implementing stream processing are provided. The system includes an application framework and applications containing dataflow graphs managed by the application framework running on a first network. The system also includes at least one circuit switch in the first network having a configuration that is controlled by the application framework, a plurality of processing nodes interconnected by the first network over one of wireline and wireless links, and a second network for providing at least one of control and additional data transfer over the first network.

Abstract: Briefly, according to an embodiment of the invention, a computing system comprises: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and for handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, for handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously. The system additionally comprises a plurality of clusters which comprise the processing nodes, and a plurality of intra-cluster communication links. The electronic packet switched networks are for handling collectives and short-lived data transfers among the processing nodes and comprises one-tenth of the bandwidth of the circuit switched networks.

Abstract: An optical assembly comprising an optical cube. A first optical transmitter chip and a first optical receiver chip are mounted on one surface of the optical cube. A first continuous printed circuit board is soldered to electrical surfaces of the first optical transmitter chip and the first optical receiver chip opposite the optical cube. A second optical transmitter chip and a second optical receiver chip are mounted on an opposite surface of the optical cube. A second continuous printed circuit board is soldered to electrical surfaces of the second optical transmitter chip and the second optical receiver chip opposite the optical cube. The first optical transmitter chip is optically aligned with the second optical receiver chip through the optical cube. The second optical transmitter chip is optically aligned with the first optical receiver chip through the optical cube.

Abstract: Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

Abstract: Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

Abstract: An optical assembly comprising an optical cube. A first optical transmitter chip and a first optical receiver chip are mounted on one surface of the optical cube. A first continuous printed circuit board is soldered to electrical surfaces of the first optical transmitter chip and the first optical receiver chip opposite the optical cube. A second optical transmitter chip and a second optical receiver chip are mounted on an opposite surface of the optical cube. A second continuous printed circuit board is soldered to electrical surfaces of the second optical transmitter chip and the second optical receiver chip opposite the optical cube. The first optical transmitter chip is optically aligned with the second optical receiver chip through the optical cube. The second optical transmitter chip is optically aligned with the first optical receiver chip through the optical cube.

Abstract: Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

Abstract: Optical components that are designed to be coupled together in modular fashion to form an optical network. The components are shaped so that a plurality of components can be coupled together to form a light cube. The components are provided with mating means to permit easy coupling. The preferred form of component is a right-angled triangular prism that can be coupled together with a similar prism to form a cube.

Abstract: A computer system that includes a plurality of processing elements for parallel computation utilizes a free-space optical network for communication between the processing elements. Such a network employs an optoelectronic switch that includes a binary H-type tree for routing signals to selected ones of an array of lasers. Hybrid repeaters are included in the optical paths to generate output optical beams colinear that are with incident input beams.

Abstract: A modular building block for supporting arrays of microlenses, microlasers and microphotodetectors, etc. in an optical beam relay system used as an optical interconnection network. The building block includes a frame member on which is mounted the array. The frame member includes a base portion that is press fitted to the smooth top surface of a plate member. The bottom surface of the plate member includes a rail portion that is secured into a groove in the support structure, such as a table, that also supports various elements of the optical interconnection network.

Abstract: A computer system that includes a plurality of processing elements for parallel computation utilizes a free-space optical network for communication between the processing elements. Such a network employs an optoelectronic switch that includes a binary H-type tree for routing signals to selected ones of an array of lasers. Hybrid repeaters are included in the optical paths to generate output optical beams colinear that are with incident input beams.

Abstract: A computer system that includes a plurality of processing elements for parallel computation utilizes a free-space optical network for communication between the processing elements. Such a network employs an optoelectronic switch that includes a binary H-type tree for routing signals to selected ones of an array of lasers. Hybrid repeaters are included in the optical paths to generate output optical beams colinear that are with incident input beams.

Abstract: An interconnection network for interconnection in parallel of a large number (N) of processing elements (PE). The network includes three serial switching stages. The first stage in which the processing elements arc grouped in r clusters of k processing elements each comprising many small fast electronic switches, one for each cluster. The second stage comprises a large number (N) of optical channels, one for each of the N processing elements. The third stage comprises k photodetectors for each of the clusters and electronic switches of the type in the first stage. Each cluster controls k light sources, one for each channel and k photodetectors in the cluster. Interconnection between processing elements in a common cluster are made solely by way of an electronic switch. Interconnection between processing elements in different clusters is made via the optical channels and one or two of the electronic switches.

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.