Abstract: Phase-locked loop (PLL) fast lock circuit and method using a second frequency controlled feedback loop to complement a primary frequency and phase controlled feedback loop. The second loop may charge a capacitor controlling input voltage to a voltage controlled oscillator (VCO) up and down faster that the primary loop, such as using up and a down charge pumps. In some cases, the second loop uses a frequency detector to detect a difference between a reference and feedback signal frequencies; and in response uses logic to control two pump up and two pump down charge pumps. The frequency detector may be configured to receive a reset signal and a lock signal. The reset signal causes the second loop to send a strong pump up charge to the capacitor without waiting for a difference in the frequencies. The lock signal causes the frequency detector to stops counting the difference in the frequencies.