Patents by Inventor Eugene George Walters, III

Eugene George Walters, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques and devices for performing arithmetic
    Patent number: 9916131
    Abstract: A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 13, 2018
    Assignee: The Penn State Research Foundation
    Inventor: Eugene George Walters, III
  • TECHNIQUES AND DEVICES FOR PERFORMING ARITHMETIC
    Publication number: 20160246571
    Abstract: A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.
    Type: Application
    Filed: October 2, 2014
    Publication date: August 25, 2016
    Inventor: Eugene George Walters, III