Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A device and method for processing a plurality of asynchronous interrupt signals provided to respective primary registers. The first provided of the signals is stored in a primary register. The primary registers are then closed to subsequently provided signals. Notice is provided of receipt of the first signal, and the primary registers are read to identify the first signal. Interrupt signals received after the primary registers are closed are stored in secondary registers.

Abstract: A system and method for transferring a designated number d of data bytes between first and second data busses. The system includes a data buffer connected between the busses, a full counter, a partial counter, and decode logic connected to the counters. The full counter counts the total number of data bytes transferred between the buffer and the first bus. The partial counter counts data bytes transferred between the buffer and the second bus. The decode logic indicates when d data bytes have been transferred between the busses.

Abstract: A data synchronizer that operates at two to four times greater clock and data rates than previous data synchronizers. By using a positive feedback, self latching gate as the first memory element, rather than a cross-coupled device such as a flip-flop, such rates are attained without inducing metastable oscillation. The positive feedback, self latching gate is far less prone to metastable oscillation since it does not have two cross-coupled devices fighting each other to resolve the proper response to an input. Instead, the self latching gate latches up if a data HIGH is present during a clock HIGH, and remains LOW otherwise. External circuitry resets the self latching gate to the LOW state before the start of each clock HIGH cycle to remove any previous latched state. The self latching gate output is then synchronously sampled by a type D flip-flop to provide a completely synchronized data output.