Abstract: A method for forming ohmic contacts for semiconductor devices, in accordance with the present invention, includes forming a layer containing metal which includes dopants integrally formed therein. The layer containing metal is patterned to form components for a semiconductor device, and a semiconductor layer is deposited for contacting the layer containing metal. The semiconductor device is annealed to outdiffuse dopants from the layer containing metal into the semiconductor layer to form ohmic contacts therebetween.

Abstract: A data and clock recovery phase locked loop circuit comprises a data transition detector block to detect transitions of random input data and to produce a window signal. A delay block delays the random input data to produce delayed random input data. A phase comparator block is connected to the delay block and compares phase of the delayed random input data with phase of a feedback signal to produce a phase compared signal. A charge pump block is connected to the phase comparator block and produces output voltage in response to the phase compared signal. A filter block is connected to the charge pump block to filter the output voltage into DC voltage. A voltage controlled oscillator is connected to the filter block to generate the clock signal which has a frequency depending on the DC voltage.

Abstract: A phase locked loop (PLL) circuit is described which uses a Schmitt trigger block (28) to achieve a very small steady state phase error at an input of a phase comparator block (21) over the entire PLL lock voltage range. The amount of hysteresis which each Schmitt trigger circuit (281, 282) in the Schmitt trigger block (28) has depends on the damping factor .zeta. of the PLL circuit as well as the temperature and voltage coefficients of a VCO's input voltage. The midpoint of the positive and the negative thresholds of the hysteresis curve of each Schmitt trigger circuit (281, 282) is set by the current voltage characteristics of charge pump circuits in a charge pump block (22). Responsive to the PLL's lock voltage (VCNT), the Schmitt trigger block (28) commands a control logic circuit (29) to turn ON or turn OFF as the case may be PMOS pump UP transistors to that of NMOS pump DOWN transistors. It is this ratio which determines the PLL's steady state phase error.

Abstract: By using a bias switch (260) to define a unique current range in a bias generator (142) for each n-bit counter output state, it is possible to control a VCO (140) which has a very wide operating frequency range. These frequency ranges must overlap to guarantee the lock irrespective of process or environmental (temperature and voltage) variations. Depending on an input value of an overall lock signal OLS to an n-bit counter (250) at the rising edge of its clock signal CLK, it is possible to scan the full spectrum of VCO frequency ranges until the lock is achieved. By comparing a switch voltage to a reference voltage Vref, it is possible to prevent the PLL from locking at the very right-hand edge of a frequency range unless it can maintain that the lock over the entire operating temperature range. By strobing a fine lock signal FLS at an integer m (>1) number of points, it is possible to prevent false lock from occurring.

Abstract: The use of a control circuit (160) with either a programmable divider or divider(s) (190) and multiplexer (200) guarantees that, irrespective of the process variations, a voltage controlled oscillator has a low gain Vin-Fout characteristic in the desired frequency range. Low-gain voltage controlled oscillators are fundamental building blocks of low-jitter phase-locked loop (PLL) systems. The programmable divider/divider(s) (190) and multiplexer (200) are placed at an output of a current controlled oscillator(s) (180). A control circuit (160) defines the optimum current range(s) in the current controlled oscillator(s) (180). In the case of when a programmable divider is used, the control circuit (160) keeps changing the division ratio of the programmable divider until the PLL eventually achieves the "locked" state. When divider(s) and a multiplexer (200) are used, the control circuit (160) keeps changing the selected multiplexer input until the "locked" state has been achieved.