Abstract: A method of operating a system on chip (SoC) includes determining to switch from a selected low-power core among a plurality of low-power cores to a high-performance core among a plurality of high-performance cores, counting the number of high-performance cores that are operating among a plurality of high-performance cores, determining a maximum operating frequency of the plurality of high-performance cores based on the counted number, and switching from the selected low-power core to the selected high-performance core based on the determined maximum operating frequency.

Abstract: A multi-cluster processing system and a method of operating a multi-cluster processing system are provided. The multi-cluster processing system includes: a first cluster including a plurality of first-type cores: a second cluster including a plurality of second-type cores; and a control unit configured to monitor loads of the first-type cores and the second-type cores, wherein when utilization of at least one of enabled first-type cores exceeds a predetermined threshold utilization of each of the first-type cores, the control unit enables at least one of disabled first-type cores in a first mode, and the control unit enables at least one of the disabled second-type cores and disables the first cluster in a second mode, wherein an amount of computation per unit of time of each of the second-type cores is greater than an amount of computation per unit of time of each of the first-type cores.

Abstract: A method of operating a system on chip (SoC) includes determining to switch from a selected low-power core among a plurality of low-power cores to a high-performance core among a plurality of high-performance cores, counting the number of high-performance cores that are operating among a plurality of high-performance cores, determining a maximum operating frequency of the plurality of high-performance cores based on the counted number, and switching from the selected low-power core to the selected high-performance core based on the determined maximum operating frequency.

Abstract: A multi-cluster processing system and a method of operating a multi-cluster processing system are provided. The multi-cluster processing system includes: a first cluster including a plurality of first-type cores: a second cluster including a plurality of second-type cores; and a control unit configured to monitor loads of the first-type cores and the second-type cores, wherein when utilization of at least one of enabled first-type cores exceeds a predetermined threshold utilization of each of the first-type cores, the control unit enables at least one of disabled first-type cores in a first mode, and the control unit enables at least one of the disabled second-type cores and disables the first cluster in a second mode, wherein an amount of computation per unit of time of each of the second-type cores is greater than an amount of computation per unit of time of each of the first-type cores.

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract: In a split gate type flash memory device, and a method of manufacturing the same, the device includes a memory cell array having a memory cell uniquely determined by a contact of a corresponding bit line and a corresponding word line, a floating gate formed on a semiconductor substrate to constitute the memory cell, the floating gate having a horizontal surface parallel to a main surface of the substrate, a vertical surface perpendicular to the main surface of the substrate, and a curved surface extending between the horizontal and vertical surfaces, a control gate formed over the curved surface of the floating gate in an area defined by an angle range of less than 90° between an extension line of the horizontal surface and an extension line of the vertical surface, and source and drain regions formed in an active region of the substrate.

Abstract: A method of manufacturing split-gate memory provides a control gate insulating film and the tunneling insulating film in a cell region, a high voltage gate insulating film in a high voltage region, and a low voltage gate insulating film in a low voltage region, all having different thickness. Additionally, a pre-cleaning process removes an outer sidewall portion of a spacer to form a tip portion of a floating gate that overlaps a control gate line formed proximate the floating gate.

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract: A method of manufacturing split-gate memory provides a control gate insulating film and the tunneling insulating film in a cell region, a high voltage gate insulating film in a high voltage region, and a low voltage gate insulating film in a low voltage region, all having different thickness. Additionally, a pre-cleaning process removes an outer sidewall portion of a spacer to form a tip portion of a floating gate that overlaps a control gate line formed proximate the floating gate.

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract: In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectr

Abstract: In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

Abstract: A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectr