Patents by Inventor Eui Joon Yoon
Eui Joon Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476388Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: GrantFiled: February 5, 2021Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-Joon Yoon, Dae-Young Moon, Jeong-Hwan Jang, Yongjo Park, Duk-Kyu Bae
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Publication number: 20210184075Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: ApplicationFiled: February 5, 2021Publication date: June 17, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-Joon YOON, Dae-Young MOON, Jeong-Hwan JANG, Yongjo PARK, Duk-Kyu BAE
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Patent number: 10916681Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: GrantFiled: February 8, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-Joon Yoon, Dae-Young Moon, Jeong-Hwan Jang, Yongjo Park, Duk-Kyu Bae
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Publication number: 20190189845Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: ApplicationFiled: February 8, 2019Publication date: June 20, 2019Inventors: Eui-Joon YOON, Dae-Young MOON, Jeong-Hwan JANG, Yongjo PARK, Duk-Kyu BAE
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Patent number: 10205052Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: GrantFiled: July 13, 2015Date of Patent: February 12, 2019Assignee: Seoul National University R&DB FoundationInventors: Eui-Joon Yoon, Dae-Young Moon, Jeong-Hwan Jang, Yongjo Park, Duk-Kyu Bae
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Patent number: 9978907Abstract: A semiconductor ultraviolet light emitting device includes: a substrate; a buffer layer disposed on the substrate and comprising a plurality of nanorods between which a plurality of voids are formed; a first conductive nitride layer disposed on the buffer layer and having a first conductive AlGaN layer; an active layer disposed on the first conductive nitride layer and having a quantum well including AlxInyGa1-x-yN (0?x+y?1, 0?y<0.15); and a second conductive nitride layer disposed on the active layer and having a second conductive AlGaN layer, in which the plurality of nanorods satisfy 3.5?n(?)×D/??5.0, where ? represents a wavelength of light generated by the active layer, n(?) represents a refractive index of the plurality of nanorods at a wavelength of ?, and D represents diameters of the plurality of nanorods.Type: GrantFiled: May 5, 2016Date of Patent: May 22, 2018Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jung Sub Kim, Dong Hyun Lee, Jin Sub Lee, Kyung Wook Hwang, In Su Shin, Eui Joon Yoon, Gun Do Lee, Jeong Hwan Jang
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Publication number: 20170271556Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: ApplicationFiled: July 13, 2015Publication date: September 21, 2017Applicants: Seoul National University R &DB Foundation, Hexasolution Co., Ltd.Inventors: Eui-Joon YOON, Dae-Young MOON, Jeong-Hwan JANG, Yongjo PARK, Duk-Kyu BAE
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Publication number: 20170054055Abstract: A semiconductor ultraviolet light emitting device includes: a substrate; a buffer layer disposed on the substrate and comprising a plurality of nanorods between which a plurality of voids are formed; a first conductive nitride layer disposed on the buffer layer and having a first conductive AlGaN layer; an active layer disposed on the first conductive nitride layer and having a quantum well including AlxInyGa1-x-yN (0?x+y?1, 0?y<0.15); and a second conductive nitride layer disposed on the active layer and having a second conductive AlGaN layer, in which the plurality of nanorods satisfy 3.5?n(?)×D/??5.0, where ? represents a wavelength of light generated by the active layer, n(?) represents a refractive index of the plurality of nanorods at a wavelength of ?, and D represents diameters of the plurality of nanorods.Type: ApplicationFiled: May 5, 2016Publication date: February 23, 2017Applicants: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jung Sub KIM, Dong Hyun LEE, Jin Sub LEE, Kyung Wook HWANG, In Su SHIN, Eui Joon YOON, Gun Do LEE, Jeong Hwan JANG
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Patent number: 7459359Abstract: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.Type: GrantFiled: November 6, 2006Date of Patent: December 2, 2008Assignee: Samsung Electronic Co., Ltd.Inventors: Tai-Su Park, Eui-Joon Yoon, U-In Chung, Si-Young Choi, Jong-Ho Lee
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Publication number: 20080186512Abstract: There is provided a curvature measuring apparatus and method using multiple beams. m×n multiple beams generated by an m×n laser diode (LD) array or an m×n vertical cavity surface emitting laser array having a uniform pitch are converted into multiple divergent or multiple parallel beams. The multiple beams strike and reflect from the surface of a thin film formed on a substrate Then, the multiple beams are detected by an m×n spot array in a detector such as a charge coupled device (CCD) or a CMOS image sensor. The spot spacing between the beams in the array is measured in a direction parallel to the incident plane. The spot spacing between the beams is changed by the curvature of the substrate in the direction parallel to the incident plane and the curvature may be expressed by a function including change in beam spacing, an incident angle, a distance between the surface of the thin film and the detector.Type: ApplicationFiled: August 1, 2006Publication date: August 7, 2008Inventors: Bong Kee, Eui-Joon Yoon
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Publication number: 20070292987Abstract: A method of fabricating a strained thin film semiconductor layer having less dislocation and less defects than conventional methods, or no dislocation and no defects by controlling a stress distribution in a semiconductor substrate is provided. The method includes forming a trench in a semiconductor substrate, and epitaxially growing a first hetero thin film inside the trench, the first hetero thin film having a lattice constant different from that of the semiconductor substrate, thereby forming a stressor thereinside. Then, a second hetero thin film is made to be epitaxially grown on the semiconductor substrate having the stressor formed therein, in which the second hetero thin film, thereby forming a strained thin film semiconductor layer by a stress field of the stressor.Type: ApplicationFiled: March 22, 2005Publication date: December 20, 2007Inventors: Eui-Joon Yoon, Suk-Won Hong, Hyun-Ho Shin
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Publication number: 20070066018Abstract: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.Type: ApplicationFiled: November 6, 2006Publication date: March 22, 2007Inventors: Tai-Su Park, Eui-Joon Yoon, U-In Chung, Si-Young Choi, Jong-Ho Lee
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Patent number: 7148541Abstract: A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.Type: GrantFiled: February 17, 2004Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-su Park, Eui-Joon Yoon, U-In Chung, Si-Young Choi, Jong-Ho Lee
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Publication number: 20050145932Abstract: A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.Type: ApplicationFiled: February 17, 2004Publication date: July 7, 2005Inventors: Tai-su Park, Eui-Joon Yoon, U-In Chung, Si-Young Choi, Jong-Ho Lee
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Patent number: 6723186Abstract: A method of manufacturing a metallic film consisting of giant single crystal grains is disclosed. The method includes depositing the metallic film on a substrate under an atmosphere of an inert gas and a specified additive gas to change a surface energy, grain boundary energy, or internal strain energy of the metallic film. The method also includes annealing step of the resultant of the deposition at a temperature suitable for the grain growth of the metallic film containing the additive gases. According to the method, the metallic film consisting of giant single crystal grains having a grain size whose ratio of thickness to an average grain size of the film is above 50 can be produced without depending upon the kind of substrate and deposition method.Type: GrantFiled: July 30, 2001Date of Patent: April 20, 2004Assignee: Inostek Inc.Inventors: Dong Su Lee, Dong Yeon Park, Hyun Jung Woo, Seung Hyun Kim, Jowoong Ha, Eui Joon Yoon
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Patent number: 6498097Abstract: A platinum film orientation-controlled to (111), (200) and/or (220) is provided by depositing the platinum film under an atmosphere containing an oxygen component such as O2, O3, N2O , N2+O2, or mixtures thereof as well as an inert gas (Ar, Ne, Kr, or Xe) on a substrate heated to a temperature ranged from room temperature to 700° C., and annealing to remove the gases introduced into the platinum film during the deposition thereof. The platinum film formed in this process has excellent electrical conductivity (resistivity is lower than 15 &mgr;&OHgr;-cm), good enough adhesion strength to be used for electronic devices, and does not show hillocks, voids or pinholes.Type: GrantFiled: April 13, 1998Date of Patent: December 24, 2002Assignee: Tong Yang Cement CorporationInventors: Dong Yeon Park, Dong Su Lee, Hyun Jung Woo, Dong Il Chun, Eui Joon Yoon
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Publication number: 20020015793Abstract: A method of manufacturing a metallic film consisting of giant single crystal grains is disclosed. The method includes depositing the metallic film on a substrate under an atmosphere of an inert gas and a specified additive gas to change a surface energy, grain boundary energy, or internal strain energy of the metallic film. The method also includes annealing step of the resultant of the deposition at a temperature suitable for the grain growth of the metallic film containing the additive gases. According to the method, the metallic film consisting of giant single crystal grains having a grain size whose ratio of thickness to an average grain size of the film is above 50 can be produced without depending upon the kind of substrate and deposition method.Type: ApplicationFiled: July 30, 2001Publication date: February 7, 2002Applicant: Insotek Inc.Inventors: Dong Su Lee, Dong Yeon Park, Hyun Jung Woo, Seung Hyun Kim, Jowoong Ha, Eui Joon Yoon
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Patent number: 6312567Abstract: A method of depositing a (200)-oriented platinum thin film on a substrate, including the steps of forming a oxygen containing platinum layer on the surface of a silicon wafer heated to a temperature range over room temperature and not exceeding 700° C. under a mixed gaseous atmosphere of oxygen and inert gas and annealing the substrate at a temperature between 400° C. and 1000° C. The platinum thin film formed according to the present invention in (200)-oriented and does not have any conventional defects such as hillocks or voids.Type: GrantFiled: May 27, 1999Date of Patent: November 6, 2001Assignee: Tong Yang Cement CorporationInventors: Dong Su Lee, Dong Il Chun, Dong Yeon Park, Eui Joon Yoon, Min Hong Kim, Hyun Jung Woo, Tae Soon Park
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Patent number: 6054331Abstract: A platinum film, which is used as a bottom electrode for a capacitor in a DRAM cell or a non-volatile ferroelectric memory cell, is formed in two separate processes, wherein a first thickness platinum part thereof is deposited under an inert gas atmosphere, and the second thickness platinum part is deposited under an atmosphere containing oxygen, nitrogen and/or a mixture thereof as well as an inert gas. The platinum film is annealed under a vacuum atmosphere to remove the oxygen an/or nitrogen introduced during the deposition of the second thickness platinum part. The annealed platinum film prevents formation of an oxide on a functional intermediate film such as a diffusion barrier layer or an adhesion layer, which is provided below the bottom electrode of platinum film.Type: GrantFiled: January 5, 1998Date of Patent: April 25, 2000Assignee: Tong Yang Cement CorporationInventors: Hyun Jung Woo, Dong Yeon Park, Dong Su Lee, Dong Il Chun, Eui Joon Yoon
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Patent number: 6025205Abstract: Platinum film orientation-controlled to (111), (200) and/or (220) are provided by depositing the platinum film under an atmosphere containing nitrogen as well as an inert gas (Ar, Ne, Kr, Xe) on a substrate heated to temperature ranged from room temperature to 500.degree. C., and then annealing to substantially remove nitrogen introduced into the platinum film during the deposition thereof. The platinum film formed in this process has an excellent electrical conductivity (resistivity is lower than 15 .mu..OMEGA.-cm), good enough adhesion strength to be used for electronic devices, and does not show hillocks, pores or pinholes.Type: GrantFiled: January 5, 1998Date of Patent: February 15, 2000Assignee: Tong Yang Cement CorporationInventors: Dong Yeon Park, Dong Su Lee, Hyun Jung Woo, Dong Il Chun, Eui Joon Yoon