Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

Abstract: A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.

Abstract: An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.

Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

Abstract: A method of operating a nonvolatile memory device configured to erase a memory block in sub-block units comprises detecting state information of unselected sub-blocks associated with a selected sub-block comprising selected memory cells, adjusting a read bias of the selected memory cells based on the state information, and reading data from the selected memory cells according to the adjusted read bias. The state information indicates a number of the unselected sub-blocks having a programmed state or an erased state.

Abstract: A data write method of a nonvolatile memory device is provided which includes receiving write data to be stored in selected memory cells; reading data stored in the selected memory cells; processing the write data according to a plurality of data modulation manners to generate a plurality of modulated data values; calculating the number of flip bits and the number of switching bits when the write data and the plurality of modulated data values are overwritten on the selected memory cells, each flip bit indicating that a logical value of a selected memory cell is reversed and each switching bit indicating that a logical value of a selected memory cell is switched from a first logical value to a second logical value; and selecting one of the write data and the plurality of modulated data values according to calculating the number of flip bits and the number of switching bits.

Abstract: A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition.

Abstract: A data management method of a nonvolatile memory device which includes a data cell area and a reference cell area includes selecting shared data from write data input to the memory device; generating reference data based on the shared data; and storing the write data in the data cell area and a first reference area of the reference cell area; and storing the reference data in a second reference area of the reference cell area.

Abstract: A method of operating a memory controller in a memory system including a nonvolatile memory device includes; erasing memory cells of a target memory block of the non-volatile memory device on a block basis, and then searching for a bad memory cell by a performing an erase verifying operation, comparing a threshold voltage of the bad memory cell to a reference voltage to generate comparison results, and designating as a bad area one of the entire target memory block, and a sub-block of the target memory block in response to the comparison results.

Abstract: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

Abstract: Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.

Abstract: An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation.

Abstract: A nonvolatile random access memory device includes a plurality of memory cells configured to store data therein, a plurality of reference cells separate from the memory cells, the reference cells each configured to output a corresponding reference cell signal, and a read/write circuit. The read/write circuit is configured to generate from the reference cell signals a reference signal which is variable to have a plurality of different reference levels. The read/write circuit is further configured to identify, in response to the reference signal, a logic state among a first logic state and a second logic state for each of one or more selected memory cells, and to output read data corresponding to the identified logic state.

Abstract: A method of operating a memory controller comprises receiving original data from an external source, partitioning the original data into multiple elements of unit data, changing an order of at least one element of unit data to reduce the number of occurrences of a target state among the multiple units of unit data, and controlling a non-volatile memory device to program the multiple elements of unit data having the reduced number of occurrences of the target state.

Abstract: A method of operating a memory controller in a memory system including a nonvolatile memory device includes; erasing memory cells of a target memory block of the non-volatile memory device on a block basis, and then searching for a bad memory cell by a performing an erase verifying operation, comparing a threshold voltage of the bad memory cell to a reference voltage to generate comparison results, and designating as a bad area one of the entire target memory block, and a sub-block of the target memory block in response to the comparison results.

Abstract: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

Abstract: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

Abstract: In one embodiment, the method includes overwriting a memory cell storing m-bit data to store n-bit data, where n is less than or equal to m. The memory cell has one of a first plurality of program states when storing the m-bit data, and the memory cell has one of a second plurality of program states when storing the n-bit data. The second plurality of program states include at least one program state not in the first plurality of program states.

Abstract: A data management method of a nonvolatile memory device which includes a data cell area and a reference cell area includes selecting shared data from write data input to the memory device; generating reference data based on the shared data; and storing the write data in the data cell area and a first reference area of the reference cell area; and storing the reference data in a second reference area of the reference cell area.