Patents by Inventor Eun Jung Jang
Eun Jung Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130848Abstract: Disclosed is an artificial implant comprising: a silicone shell; and a filler filling the interior of the shell, wherein at least a portion of the shell is a rupture-prevention part comprising two or more silicone layers and one or more reinforcing material layers interposed therebetween.Type: ApplicationFiled: February 11, 2022Publication date: April 25, 2024Applicant: OSSTEMIMPLANT CO., LTD.Inventors: Eun Jung SIM, Byung Hwi KIM, Min Kyoung KIM, Ju Dong SONG, II Seok JANG
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Publication number: 20240130849Abstract: Disclosed are an artificial implant and a method for manufacturing same, the artificial implant comprising: a silicone shell consisting of an upper portion, a lower portion, and a side portion; and a filler injected into the silicone shell, wherein the silicone shell includes at least one silicone layer and at least one reinforcing layer, the reinforcing layer being provided on at least a portion of the lower portion and the side portion of the silicone shell, or the silicone shell includes a layered structure having a step.Type: ApplicationFiled: February 11, 2022Publication date: April 25, 2024Applicant: OSSTEMIMPLANT CO., LTD.Inventors: Eun Jung SIM, Byung Hwi KIM, Min Kyoung KIM, Ju Dong SONG, ll Seok JANG
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Publication number: 20240083466Abstract: The present disclosure relates to a driving mode switching device and a driving mode switching method. Particularly, the driving mode switching device according to the present disclosure comprises: a driving mode switching determination unit for determining to switch a driving mode of a vehicle to either an autonomous driving mode or a manual driving mode on the basis of at least one from among driving information, detection information, and driver detection information; and a driving mode switching unit for controlling a transition section in which the driving mode is switched and/or the ratio of turning control signals in the driving modes on the basis of at least one from among the driving information, the detection information, and the driver detection information when it is determined that the driving mode is to be switched, and switching the driving mode by changing the turning control signal.Type: ApplicationFiled: September 22, 2020Publication date: March 14, 2024Inventors: Eun Ho JANG, Ki Sung JO, Hyun Jung KIM
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Patent number: 9018185Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: GrantFiled: September 24, 2013Date of Patent: April 28, 2015Assignee: Postech Academy-Industry FoundationInventors: Jung Hwan Lee, Soon Hag Kim, Mi-Jin Kwon, Hyungu Kang, Sung Ho Ryu, Jong In Kim, Youndong Kim, Young Chan Chae, Sung Key Jang, Jong Hun Im, Sun Hak Lee, Hye Jung Lee, Eun Jung Jang, Ki Seok Kim
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Patent number: 9018186Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: GrantFiled: September 24, 2013Date of Patent: April 28, 2015Assignee: Postech Academy-Industry FoundationInventors: Jung Hwan Lee, Soon Hag Kim, Mi-Jin Kwon, Hyungu Kang, Sung Ho Ryu, Jong In Kim, Youndong Kim, Young Chan Chae, Sung Key Jang, Jong Hun Im, Sun Hak Lee, Hye Jung Lee, Eun Jung Jang, Ki Seok Kim
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Publication number: 20140213636Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: September 24, 2013Publication date: July 31, 2014Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: JUNG HWAN LEE, SOON HAG KIM, MI-JIN KWON, HYUNGU KANG, SUNG HO RYU, JONG IN KIM, YOUNDONG KIM, YOUNG CHAN CHAE, SUNG KEY JANG, JONG HUN IM, SUN HAK LEE, HYE JUNG LEE, EUN JUNG JANG, KI SEOK KIM
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Publication number: 20140093886Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: September 24, 2013Publication date: April 3, 2014Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: JUNG HWAN LEE, SOON HAG KIM, MI-JIN KWON, HYUNGU KANG, SUNG HO RYU, JONG IN KIM, YOUNDONG KIM, YOUNG CHAN CHAE, SUNG KEY JANG, JONG HUN IM, SUN HAK LEE, HYE JUNG LEE, EUN JUNG JANG, KI SEOK KIM
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Patent number: 8569252Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: GrantFiled: April 14, 2010Date of Patent: October 29, 2013Assignees: Postech Academy-Industry Foundation, PoscoInventors: Jung-Hwan Lee, Soon-Hag Kim, Mi-Jin Kwon, Hyun-Gu Kang, Sung-Ho Ryu, Jong-In Kim, Youn-Dong Kim, Young-Chan Chae, Sung-Key Jang, Jong-Hun Im, Sun-Hak Lee, Hye-Jung Lee, Eun-Jung Jang, Ki-Seok Kim
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Patent number: 8124756Abstract: A method for preparing amino linker oligonucleotides is provided. More specifically, a method of preparing 5?-amino-linker oligonucleotides comprising the steps of: introducing an amino linker having a protecting group into the 5? terminus of an oligonucleotide; and removing the protecting group from the amino linker oligonucleotide by contacting with acetic acid and 2,2,2-trifluoroethanol is provided. The amino protecting group is efficiently removed from the amino linker oligonucleotides, and thereby achieving a high yield of the amino linker oligonucleotides.Type: GrantFiled: September 15, 2009Date of Patent: February 28, 2012Assignees: Postech Academy-Industry Foundation, PoscoInventors: Jung-Hwan Lee, Hyun-Gu Kang, Sung-Ho Ryu, Jong-In Kim, Sun-Hak Lee, Hye-Jung Lee, Eun-Jung Jang
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Publication number: 20100317723Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: April 14, 2010Publication date: December 16, 2010Applicants: POSTECH ACADEMY-INDUSTRY FOUDATION, POSCOInventors: JUNG-HWAN LEE, SOON-HAG KIM, MI-JIN KWON, HYUN-GU KANG, SUNG-HO RYU, JONG-IN KIM, YOUN-DONG KIM, YOUNG-CHAN CHAE, SUNG-KEY JANG, JONG-HUN IM, SUN-HAK LEE, HYE-JUNG LEE, EUN-JUNG JANG, KI-SEOK KIM
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Publication number: 20100093994Abstract: A method for preparing amino linker oligonucleotides is provided, wherein an amino protecting group is efficiently removed from the amino linker oligonucleotides protected by the protecting group, and thereby achieving a high yield of the amino linker oligonucleotides.Type: ApplicationFiled: September 15, 2009Publication date: April 15, 2010Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, POSCOInventors: Jung-Hwan LEE, Hyun-Gu Kang, Sung-Ho Ryu, Jong-In Kim, Sun-Hak Lee, Hye-Jung Lee, Eun-Jung Jang
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Patent number: 7542358Abstract: A delay locked loop(DLL) includes a phase detector for detecting phase difference between input clock signals and feedback clock signals, and outputting phase detection signals according to results of the detection, a delay line for delaying the input clock signals in response to first and second delay control signals, and outputting delay clock signals, a delay controller for generating the first and the second delay control signals in response to the phase detection signals, and a delay model for delaying reference clock signals during predetermined time, and outputting the delayed signals as the feedback clock signals.Type: GrantFiled: September 28, 2006Date of Patent: June 2, 2009Assignee: Hynix Semiconductor Inc.Inventor: Eun Jung Jang
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Patent number: 7516382Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.Type: GrantFiled: December 1, 2005Date of Patent: April 7, 2009Assignee: Hynix Semiconductor Inc.Inventors: Hyung-Dong Lee, Eun-Jung Jang
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Publication number: 20070263460Abstract: A DLL with a reduced size, a semiconductor memory device including the DLL and a locking operation method of the DLL that includes a phase detector, a delay line, a delay controller, a delay circuit and an output buffer. The phase detector detects phase difference between input clock signals and feedback clock signals, and outputs phase detection signals according to results of the detection. The delay circuit delays reference clock signals during predetermined time and outputs the delayed signals as feedback clock signals. The output buffer outputs internal clock signals in response to delay clock signals. The reference clock signals are generated by one of circuits that exist in an actual output path of the internal clock signals. Accordingly, it is possible to reduce skew between the data strobe signals/the output data signals and the external clock signals, which may occur according to conditions in manufacturing processes, and to reduce the occupation area of the DLL.Type: ApplicationFiled: September 28, 2006Publication date: November 15, 2007Inventor: Eun Jung Jang
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Publication number: 20060150044Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.Type: ApplicationFiled: December 1, 2005Publication date: July 6, 2006Inventors: Hyung-Dong Lee, Eun-Jung Jang
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Patent number: 6990032Abstract: A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh bufferType: GrantFiled: March 30, 2004Date of Patent: January 24, 2006Assignee: Hynix Semiconductor Inc.Inventor: Eun-Jung Jang
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Patent number: 6985401Abstract: A memory device minimizes the skew between an external clock and a DQS (or DQ) after the locking state by regulating a delay ratio of a replica delay model to compensate errors of process, temperature or voltage change. The memory device comprises: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer. Here, the DLL comprises a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.Type: GrantFiled: June 1, 2004Date of Patent: January 10, 2006Assignee: Hynix Semiconductor Inc.Inventors: Eun Jung Jang, Hyung Dong Lee
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Publication number: 20050195674Abstract: A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh bufferType: ApplicationFiled: March 30, 2004Publication date: September 8, 2005Inventor: Eun-Jung Jang