Patents by Inventor Eun Jung Jo
Eun Jung Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240083466Abstract: The present disclosure relates to a driving mode switching device and a driving mode switching method. Particularly, the driving mode switching device according to the present disclosure comprises: a driving mode switching determination unit for determining to switch a driving mode of a vehicle to either an autonomous driving mode or a manual driving mode on the basis of at least one from among driving information, detection information, and driver detection information; and a driving mode switching unit for controlling a transition section in which the driving mode is switched and/or the ratio of turning control signals in the driving modes on the basis of at least one from among the driving information, the detection information, and the driver detection information when it is determined that the driving mode is to be switched, and switching the driving mode by changing the turning control signal.Type: ApplicationFiled: September 22, 2020Publication date: March 14, 2024Inventors: Eun Ho JANG, Ki Sung JO, Hyun Jung KIM
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Patent number: 11650203Abstract: Disclosed are a one-pot biosensor and an immunoassay method using the same. The one-pot biosensor includes a photocatalyst substrate deposited with metal nanoparticles; and a reaction pad which is disposed on an upper surface of the photocatalyst substrate and includes a first binding material-fluorescent material complex specifically binding to a molecule to be detected, and the immunoassay method using the same. The one-pot biosensor may detect a target by once solution injection and has a size enough to be portable. Accordingly, since the one-pot biosensor can detect the target by only once solution injection without a washing step, because of a sensor platform capable of being easily used by an individual other than a diagnostic expert, it is predicted to be positioned as a means capable of confirming the health condition of the individual without seeing the doctor, such as a pregnancy diagnostic kit which has been currently commercialized.Type: GrantFiled: June 29, 2021Date of Patent: May 16, 2023Assignee: GIST (Gwangju Institute of Science and Technology)Inventors: Min Gon Kim, Ki Hyeun Kim, Eun Jung Jo, Dong Gu Hong
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Publication number: 20210405042Abstract: Disclosed are a one-pot biosensor and an immunoassay method using the same. The one-pot biosensor includes a photocatalyst substrate deposited with metal nanoparticles; and a reaction pad which is disposed on an upper surface of the photocatalyst substrate and includes a first binding material-fluorescent material complex specifically binding to a molecule to be detected, and the immunoassay method using the same. The one-pot biosensor may detect a target by once solution injection and has a size enough to be portable. Accordingly, since the one-pot biosensor can detect the target by only once solution injection without a washing step, because of a sensor platform capable of being easily used by an individual other than a diagnostic expert, it is predicted to be positioned as a means capable of confirming the health condition of the individual without seeing the doctor, such as a pregnancy diagnostic kit which has been currently commercialized.Type: ApplicationFiled: June 29, 2021Publication date: December 30, 2021Applicant: GIST (Gwangju Institute of Science and Technology)Inventors: Min Gon KIM, Ki Hyeun KIM, Eun Jung JO, Dong Gu HONG
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Patent number: 10871496Abstract: Disclosed is a platform detecting glycated hemoglobin as an indicator for diabetes in the blood based on upconverting nanoparticles excited by near-infrared light and luminescence resonance energy transfer.Type: GrantFiled: December 28, 2015Date of Patent: December 22, 2020Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Min-Gon Kim, Hyo-Young Mun, Eun-Jung Jo
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Patent number: 10734324Abstract: A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.Type: GrantFiled: October 25, 2018Date of Patent: August 4, 2020Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yun Tae Lee, Eun Jung Jo, Han Kim
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Patent number: 10667419Abstract: There are provided an electronic component module in which an external terminal is disposed outwardly from a mold part by a plating process and a manufacturing method thereof. The electronic component module includes a substrate, at least one electronic component mounted on the substrate, a mold part sealing the electronic component, and at least one connection conductor having one end bonded to one surface of the substrate and formed in the mold part so as to penetrate through the mold part. The connection conductor is formed to have a form in which horizontal cross-sectional areas of the connection conductor are gradually reduced toward the substrate and includes at least one step.Type: GrantFiled: November 29, 2017Date of Patent: May 26, 2020Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Do Jae Yoo, Eun Jung Jo, Jae Hyun Lim
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Patent number: 10580759Abstract: A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.Type: GrantFiled: October 4, 2018Date of Patent: March 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun Jung Jo, Han Kim, Yoon Seok Seo
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Patent number: 10483197Abstract: A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.Type: GrantFiled: April 25, 2018Date of Patent: November 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun Jung Jo, Hyung Joon Kim, Han Kim, Bo Min Jeong
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Publication number: 20190326223Abstract: A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.Type: ApplicationFiled: October 25, 2018Publication date: October 24, 2019Inventors: Yun Tae LEE, Eun Jung JO, Han KIM
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Publication number: 20190267351Abstract: A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.Type: ApplicationFiled: October 4, 2018Publication date: August 29, 2019Inventors: Eun Jung JO, Han KIM, Yoon Seok SEO
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Publication number: 20190189549Abstract: A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.Type: ApplicationFiled: April 25, 2018Publication date: June 20, 2019Inventors: Eun Jung Jo, Hyung Joon Kim, Han Kim, Bo Min Jeong
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Publication number: 20190189600Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.Type: ApplicationFiled: April 25, 2018Publication date: June 20, 2019Inventors: Jae Hyun LIM, Han KIM, Eun Jung JO, Jung Ho SHIM, Sang Jong LEE, Hyung Joon KIM
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Patent number: 10325891Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.Type: GrantFiled: April 25, 2018Date of Patent: June 18, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae Hyun Lim, Han Kim, Eun Jung Jo, Jung Ho Shim, Sang Jong Lee, Hyung Joon Kim
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Publication number: 20190164893Abstract: A semiconductor package includes: an interposer having a first surface and a second surface and including a first redistribution layer; a semiconductor chip having an active surface having connection electrodes disposed thereon and an inactive surface and disposed on the interposer so that the inactive surface faces the second surface of the interposer; an encapsulant disposed on the second surface of the interposer, including a photosensitive insulating material, and having a first region covering the semiconductor chip and a second region positioned around the semiconductor chip; and a second redistribution layer including second vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer, and second wiring patterns disposed on the encapsulant and having integrated structures with the second vias and the through-vias.Type: ApplicationFiled: March 29, 2018Publication date: May 30, 2019Inventors: Han KIM, Eun Jung JO, Jung Ho SHIM
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Patent number: 10304807Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: GrantFiled: April 12, 2018Date of Patent: May 28, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
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Patent number: 10157886Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: GrantFiled: February 21, 2017Date of Patent: December 18, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
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Patent number: 10121769Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: GrantFiled: February 21, 2017Date of Patent: November 6, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
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Patent number: 10096552Abstract: A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.Type: GrantFiled: August 29, 2017Date of Patent: October 9, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Han Kim, Eun Jung Jo, Jung Ho Shim
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Publication number: 20180233489Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: Dae Hyun PARK, Eun Jung JO, Sung Won JEONG, Han KIM, Mi Ja HAN
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Publication number: 20180190591Abstract: A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.Type: ApplicationFiled: August 29, 2017Publication date: July 5, 2018Inventors: Han KIM, Eun Jung JO, Jung Ho SHIM