Patents by Inventor Eun-Kyoung Kwon
Eun-Kyoung Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10020231Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: GrantFiled: February 27, 2017Date of Patent: July 10, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Hee Jeon, Eun-Kyoung Kwon, Il-Ryong Kim, Han-Gu Kim, Woo-Jin Seo, Ki-Tae Lee
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Publication number: 20170170075Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-Hee JEON, Eun-Kyoung KWON, II-Ryong KIM, Han-Gu KIM, Woo-Jin SEO, Ki-Tae LEE
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Patent number: 9620502Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: GrantFiled: February 12, 2014Date of Patent: April 11, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Hee Jeon, Eun-Kyoung Kwon, Il-Ryong Kim, Han-Gu Kim, Woo-Jin Seo, Ki-Tae Lee
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Patent number: 9139703Abstract: Provided is a method of solubilizing a poorly soluble/insoluble active material through formation of an oligomer composite, in which a structure having a hydrophobic cavity structure is formed by using oligomers derived from two types of hydrophilic natural polymers and a poorly soluble/insoluble component is encapsulated in the cavity structure, and thus, self-aggregation of the poorly soluble/insoluble material is prevented and simultaneously, thermodynamic stability increases to effectively solubilize the poorly soluble/insoluble material.Type: GrantFiled: October 15, 2010Date of Patent: September 22, 2015Assignee: BIOGENICS, INC.Inventors: Chul-Hwan Kim, Seung-Hak Ko, Jae-Seong Shim, Eun-Kyoung Kwon, Yong-Han Choi
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Publication number: 20140332883Abstract: A fin-shaped active region is defined on a substrate. First and second gate electrodes crossing the fin-shaped active region are arranged. A dummy gate electrode is formed between the first and second gate electrodes. A first drain region is formed between the first gate electrode and the dummy gate electrode. A second drain region is formed between the dummy gate electrode and the second gate electrode. A source region facing the second drain region is formed. A first drain plug relatively close to the dummy gate electrode, relatively far from the second gate electrode, and connected to the second drain region is formed. The second gate electrode is arranged between the second drain region and the source region. Each of the first and second gate electrodes covers a side surface of the fin-shaped active region.Type: ApplicationFiled: November 25, 2013Publication date: November 13, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-Kyoung Kwon, Hee-Soo Kang, Han-Gu Kim, Woo-Jin Seo, Ki-Tae Lee, Jae-Gon Lee, Chan-Hee Jeon
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Publication number: 20140306296Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: ApplicationFiled: February 12, 2014Publication date: October 16, 2014Inventors: Chan-Hee JEON, Eun-Kyoung KWON, Il-Ryong KIM, Han-Gu KIM, Woo-Jin SEO, Ki-Tae LEE
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Publication number: 20120219604Abstract: Provided is a method of solubilizing a poorly soluble/insoluble active material through formation of an oligomer composite, in which a structure having a hydrophobic cavity structure is formed by using oligomers derived from two types of hydrophilic natural polymers and a poorly soluble/insoluble component is encapsulated in the cavity structure, and thus, self-aggregation of the poorly soluble/insoluble material is prevented and simultaneously, thermodynamic stability increases to effectively solubilize the poorly soluble/insoluble material.Type: ApplicationFiled: October 15, 2010Publication date: August 30, 2012Inventors: Chul-Hwan Kim, Seung-Hak Ko, Jae-Seong Shim, Eun-Kyoung Kwon, Yong-Han Choi
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Patent number: 7354813Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.Type: GrantFiled: June 1, 2005Date of Patent: April 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Gue-Hyung Kwon, Eun-Kyoung Kwon
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Publication number: 20070164310Abstract: An electrostatic discharge element includes a first diode and a second diode. The first diode has a first well region formed in a substrate, a P-type ion-implanted region formed in the first well region, an N-type ion-implanted region formed in the first well region and spaced from the P-type ion-implanted region by a predetermined first distance, and a first intermediate layer formed on a portion of the first well region corresponding to the predetermined first distance. The second diode has a second well region form in the substrate, a P-type ion-implanted region formed in the second well region, an N-type ion-implanted region formed in the second well region and spaced from the P-type ion-implanted region by a predetermined second distance, and a second intermediate layer formed on a portion of the second well region corresponding to the predetermined second distance.Type: ApplicationFiled: January 18, 2007Publication date: July 19, 2007Inventor: Eun-Kyoung Kwon
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Publication number: 20050205928Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.Type: ApplicationFiled: June 1, 2005Publication date: September 22, 2005Inventors: Gue-Hyung Kwon, Eun-Kyoung Kwon
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Patent number: 6914305Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.Type: GrantFiled: September 23, 2002Date of Patent: July 5, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Gue-Hyung Kwon, Eun-Kyoung Kwon
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Publication number: 20030058027Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.Type: ApplicationFiled: September 23, 2002Publication date: March 27, 2003Inventors: Gue-Hyung Kwon, Eun-Kyoung Kwon