Patents by Inventor Eun-Soo Nam
Eun-Soo Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130156362Abstract: Provided is a core which reduces optic splice loss between discontinuous optical waveguides.Type: ApplicationFiled: September 12, 2012Publication date: June 20, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Duk Jun KIM, Jong-Hoi Kim, Joong-Seon Choe, Chun Ju Youn, Kwang-Seong Choi, Yong-Hwan Kwon, Eun Soo Nam
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Publication number: 20130153962Abstract: The inventive concept provides avalanche photo diodes and methods of manufacturing the same. The avalanche photo diode may include a substrate, a light absorption layer formed on the substrate, a clad layer formed on the light absorption layer, an active region formed in the clad layer, a guard ring region formed around the active region, and an insulating region formed between the guard ring region and the active region.Type: ApplicationFiled: September 6, 2012Publication date: June 20, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Sik SIM, Kisoo Kim, Bongki Mheen, MyoungSook Oh, Yong-Hwan Kwon, Eun Soo Nam
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Publication number: 20130146944Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.Type: ApplicationFiled: August 23, 2012Publication date: June 13, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue Min, Jong Min Lee, Seong-II Kim, Dong Min Kang, Ho Kyun Ahn, Jong-Won Lim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20130134554Abstract: Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.Type: ApplicationFiled: September 14, 2012Publication date: May 30, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-il KIM, Sang-Heung LEE, Jong-Won LIM, Hyung Sup YOON, Jongmin LEE, Byoung-Gue MIN, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8421538Abstract: Provided is a feedback amplifier including: an amplification circuit unit to generate an output voltage by amplifying an input voltage inputted through an input terminal; an output circuit unit to output the generated output voltage through an output terminal; a feedback circuit unit to control the gain of the amplification circuit unit by determining a total feedback resistance value using an external control signal and controlling an input current while the total feedback resistance value is determined; and a bias circuit unit to apply a bias voltage to the feedback circuit unit.Type: GrantFiled: July 19, 2011Date of Patent: April 16, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20130069173Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.Type: ApplicationFiled: August 23, 2012Publication date: March 21, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Woo Jin CHANG, Jong Won LIM, Ho Kyun AHN, Sang Choon KO, Sung Bum BAE, Chull Won JU, Young Rak PARK, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20130069127Abstract: A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.Type: ApplicationFiled: July 24, 2012Publication date: March 21, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho Kyun AHN, Jong-Won Lim, Sung Bum Bae, Sang Choon Ko, Young Rak Park, Woo Jin Chang, Jae Kyoung Mun, Eun Soo Nam, Jeong Jin Kim, Chull Won Ju
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Publication number: 20130020649Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: ApplicationFiled: July 13, 2012Publication date: January 24, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung Bum BAE, Eun Soo NAM, Jae Kyoung MUN, Sung Bock KIM, Hae Cheon KIM, Chull Won JU, Sang Choon KO, Jong-Won LIM, Ho Kyun AHN, Woo Jin CHANG, Young Rak PARK
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Patent number: 8338868Abstract: An image sensor with a shared photodiode is provided. The image sensor includes at least two unit pixels, each of which includes a photodiode, a diffusion region which gathers electrons from the photodiode, a transfer transistor which connects the photodiode with the diffusion region, and a readout circuit which reads out a signal from the diffusion region. Photodiodes of neighboring unit pixels are disposed symmetrically to be adjacent to one another to form a shared photodiode. The image sensor does not have a STI region which causes a dark current restricting its performance and does not require a basic minimum design factor (a distance or an area) related to a STI region. A region corresponding to a STI region may be used as a region of a photodiode or for additional pixel scaling. Therefore, a limitation in scaling of a photodiode is overcome, and pixel performance is improved in spite of pixel scaling.Type: GrantFiled: November 25, 2009Date of Patent: December 25, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Bong Ki Mheen, Albert J. P. Theuwissen, Jae Sik Sim, Mi Ran Park, Yong Hwan Kwon, Eun Soo Nam
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Patent number: 8304895Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.Type: GrantFiled: April 21, 2010Date of Patent: November 6, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Woojin Chang, Soon Il Yeo, Hae Cheon Kim, Eun Soo Nam
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Patent number: 8304859Abstract: Provided is an optical interconnection device. The optical interconnection device include: a first semiconductor chip disposed on a germanium-on-insulator (GOI) substrate; a light emitter on the GOI substrate, the light emitter receiving an electrical signal from the first semiconductor chip and outputting a light signal; a light detector on the GOI substrate, the light detector sensing the light signal and converting the sensed light signal into an electrical signal; and a second semiconductor chip on the GOI substrate, the second semiconductor chip receiving the electrical signal from the light detector.Type: GrantFiled: July 30, 2010Date of Patent: November 6, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20120248404Abstract: The present disclosure relates to a gallium-nitride light emitting diode and a manufacturing method thereof and the gallium-nitride light emitting diode includes an n-type nitride semiconductor layer formed on a substrate; an active layer formed on the n-type nitride semiconductor layer; a p-type doped intermediate layer formed on the active layer; and a p-type nitride semiconductor layer formed on the intermediate layer.Type: ApplicationFiled: February 28, 2012Publication date: October 4, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong Moo LEE, Han Youl RYU, Eun Soo NAM, Sung Bum BAE
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Patent number: 8272789Abstract: Provided are an adapter assembly and method for compensating optical fibers for a length difference. The adapter assembly includes a first adapter, a second adapter, and a member. The first adapter is configured to be connected to at least one optical communication unit. The second adapter is configured to be connected to at least another optical communication unit and be coupled to the first adapter. The member is configured to be interposed between the first and second adapters for providing an optical signal transmission path between the optical communication units. Owing to the member, a length difference between optical fibers can be compensated for.Type: GrantFiled: May 26, 2010Date of Patent: September 25, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Joong-Seon Choe, Yong-Hwan Kwon, Chun Ju Youn, Jong-Hoi Kim, Kwang-Seong Choi, Eun Soo Nam
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Publication number: 20120162373Abstract: Disclosed is a system of a dynamic range three-dimensional image, including: an optical detector including a gain control terminal capable of controlling an optical amplification gain; a pixel detecting module for detecting a pixel signal for configuring an image by receiving an output of the optical detector; a high dynamic range (HDR) generating module for acquiring a dynamic range image by generating a signal indicating a saturation degree of the pixel signal and combining the pixel signal based on the pixel signal detected by the pixel detecting module; and a gain control signal generating module generating an output signal for supplying required voltage to the gain control terminal of the optical detector based on the magnitude of the signal indicating the saturation degree of the pixel signal.Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Bongki MHEEN, Ki-Jun Sung, Jae-Sik Sim, Kisoo Kim, MyoungSook Oh, Yong-Hwan Kwon, Eun Soo Nam
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Publication number: 20120156826Abstract: A method includes: forming an epitaxy wafer by growing a light absorbing layer, a grading layer, an electric field buffer layer, and an amplifying layer on the front surface of a substrate in sequence; forming a diffusion control layer on the amplifying layer; forming a protective layer for protecting the diffusion control layer on the diffusion control layer; forming an etching part by etching from the protective layer to a predetermined depth of the amplifying layer; forming a first patterning part by patterning the protective layer; forming a junction region and a guardring region at the amplifying layer by diffusing a diffusion material to the etching part and the first patterning part; removing the diffusion control layer and the protective layer and forming a first electrode connected to the junction region on the amplifying layer; and forming a second electrode on the rear surface of the substrate.Type: ApplicationFiled: October 14, 2011Publication date: June 21, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae Sik SIM, Ki Soo KIM, Bong Ki MHEEN, Myoung Sook OH, Yong Hwan KWON, Eun Soo NAM
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Publication number: 20120155887Abstract: Disclosed are a method and an apparatus for transmitting and receiving coherent optical OFDM.Type: ApplicationFiled: November 22, 2011Publication date: June 21, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chun Ju YOUN, Yong-Hwan Kwon, Duk Jun Kim, Jong-Hoi Kim, Joong-Seon Choe, Kwang-Seong Choi, Eun Soo Nam
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Publication number: 20120153361Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: ApplicationFiled: November 30, 2011Publication date: June 21, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Byoung-Gue Min, Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20120146107Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.Type: ApplicationFiled: October 17, 2011Publication date: June 14, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Won LIM, Hokyun Ahn, Dong Min Kang, Woojin Chang, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20120132792Abstract: An exemplary embodiment of the present disclosure provides an optical module including: an optical hybrid including a metal optical waveguide; a photo detector configured to receive light; and a platform including an optical hybrid supporting section for supporting the optical hybrid, a photo detector supporting section for supporting the photo detector, and an inclined surface configured to change a propagation direction of light emitted from the optical hybrid, and configured to combine the optical hybrid and the photo detector.Type: ApplicationFiled: October 21, 2011Publication date: May 31, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Joong-Seon Choe, Jong-Hoi Kim, Chun Ju Youn, Duk Jun Kim, Kwang-Seong Choi, Yong-Hwan Kwon, Eun Soo Nam
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Patent number: 8183612Abstract: Provided are an optical receiver and a method of forming the same. The optical receiver includes a lens, a photo detector, and a hetero-junction bipolar transistor. The lens is attached to a backside of a substrate. The photo detector is disposed on a top surface of the substrate. The hetero-junction bipolar transistor is disposed on the top surface of the substrate. The lens condenses an incident optical signal to transmit the condensed optical signal to the photo detector.Type: GrantFiled: July 7, 2009Date of Patent: May 22, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Young-Jun Chong, Eun-Soo Nam, Jae-Sik Sim, Yong-Hwan Kwon, Bong-Ki Mheen