Patents by Inventor Eun Souk Lee

Eun Souk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Latch structure and bit line sense amplifier structure including the same
    Patent number: 8111569
    Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: February 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kang Seol Lee, Eun Souk Lee
  • Semiconductor memory device
    Patent number: 7782647
    Abstract: A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output line and the first local input/output line in response to a first switch control signal, and a dummy input/output switch which is connected to a second local input/output line but is not connected to the segment input/output line.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Souk Lee, Kang-Seol Lee
  • LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME
    Publication number: 20100097873
    Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.
    Type: Application
    Filed: December 22, 2009
    Publication date: April 22, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kang Seol Lee, Eun Souk Lee
  • Latch structure and bit line sense amplifier structure including the same
    Patent number: 7646651
    Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: January 12, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kang Seol Lee, Eun Souk Lee
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20090059643
    Abstract: A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output line and the first local input/output line in response to a first switch control signal, and a dummy input/output switch which is connected to a second local input/output line but is not connected to the segment input/output line.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 5, 2009
    Inventors: Eun-Souk Lee, Kang-Seol Lee
  • LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME
    Publication number: 20080225605
    Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.
    Type: Application
    Filed: December 21, 2007
    Publication date: September 18, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kang Seol Lee, Eun Souk Lee