Abstract: A lens module assembly optimization method includes: in preparing a lens module including assembled N lenses respectively formed in cavities: receiving characteristic information of at least N lenses respectively formed in N cavity groups each including a respective plurality of cavities; and processing information for selecting N cavities from the N cavity groups, based on the characteristic information. A past cavity selection result, a fitness function configured based on data of the assembled N lenses or data of the prepared lens module according to the past cavity selection result, and a genetic algorithm are received or stored.

Abstract: The present disclosure relates to an antibody binding specifically to CD55 or an antigen-binding fragment thereof; and a composition for preventing, treating and/or diagnosing cancer containing the same. The antibody of the present disclosure may be used as an effective therapeutic composition for various CD55-mediated diseases since it shows high binding ability and inhibitory effect for the CD55 protein which promotes tumor growth by inhibiting the complement immune mechanism. In addition, the antibody of the present disclosure may be usefully used as an effective therapeutic adjuvant that fundamentally removes drug resistance and remarkably improves therapeutic responsiveness in various diseases in which resistance to therapeutic agents with CDC (complement-dependent cytotoxicity) as a mechanism of action has been induced due to overexpression of CD55.

Abstract: A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at the same time a gate capping insulating layer of the cell array region, the active region of the NMOS transistor and the gate node contact region remains at a predetermined thickness by etching the spacer. And then, by performing an ion implantation procedure on the entire surface, the direct pad polysilicon layer and the buried pad polysilicon layer are simultaneously ion-implanted.

Abstract: The present invention is directed to a semiconductor structure, and a fabrication technique for forming such a structure, configured to confine and prevent expansion of cracking of the insulating layer below a bonding pad, that are generated as a result of the bonding process. In a first embodiment, the present invention includes a vertical frame, formed, for example of conductive material, surrounding the outer perimeter of the bonding pad, and extending through an underlying insulating layer. A horizontal frame lies below the vertical frame. Together, the vertical frame and horizontal frame confine cracks emanating below the bonding pad to within the frame region. In a second embodiment, horizontal and vertical portions of the frame are formed by a conductive layer provided in an opening formed in the insulating layer. Since the isolation frame prevents cracks from expanding into surrounding regions of the integrated circuit, overall process yield and reliability are improved.

Abstract: The present invention is directed to a semiconductor structure, and a fabrication technique for forming such a structure, configured to confine and prevent expansion of cracking of the insulating layer below a bonding pad, that are generated as a result of the bonding process. In a first embodiment, the present invention includes a vertical frame, formed, for example of conductive material, surrounding the outer perimeter of the bonding pad, and extending through an underlying insulating layer. A horizontal frame lies below the vertical frame. Together, the vertical frame and horizontal frame confine cracks emanating below the bonding pad to within the frame region. In a second embodiment, horizontal and vertical portions of the frame are formed by a conductive layer provided in an opening formed in the insulating layer. Since the isolation frame prevents cracks from expanding into surrounding regions of the integrated circuit, overall process yield and reliability are improved.

Abstract: A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at the same time a gate capping insulating layer of the cell array region, the active region of the NMOS transistor and the gate node contact region remains at a predetermined thickness by etching the spacer. And then, by performing an ion implantation procedure on the entire surface, the direct pad polysilicon layer and the buried pad polysilicon layer are simultaneously ion-implanted.