Patents by Inventor Eung-Rim Hwang
Eung-Rim Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10879461Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: GrantFiled: December 5, 2019Date of Patent: December 29, 2020Assignee: SK hynix Inc.Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
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Patent number: 10793812Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a material layer over a substrate; forming a material pattern by etching the material layer, the etching providing an etch residue on sidewalls of the material pattern; and removing the etch residue, wherein removing of the etch residue includes performing a cleaning process using a cleaning composition including water and a fluorine-containing compound or an amine, and having a pH in a range of 7 to 14.Type: GrantFiled: March 1, 2018Date of Patent: October 6, 2020Assignee: SK hynix Inc.Inventors: Ok-Min Moon, Sang-Soo Kim, Eung-Rim Hwang, Jong-Young Cho
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Publication number: 20200111956Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Hyo June KIM, Chi Ho KIM, Sang Hoon CHO, Eung Rim HWANG
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Patent number: 10535819Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: GrantFiled: March 30, 2018Date of Patent: January 14, 2020Assignee: SK HYNIX INC.Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
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Patent number: 10381410Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.Type: GrantFiled: November 1, 2018Date of Patent: August 13, 2019Assignee: SK HYNIX INC.Inventors: Chi-Ho Kim, Eung-Rim Hwang, Sang-Hoon Cho
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Publication number: 20190221612Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.Type: ApplicationFiled: November 1, 2018Publication date: July 18, 2019Inventors: Chi-Ho KIM, Eung-Rim HWANG, Sang-Hoon CHO
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Publication number: 20190088871Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.Type: ApplicationFiled: March 30, 2018Publication date: March 21, 2019Inventors: Hyo June KIM, Chi Ho KIM, Sang Hoon CHO, Eung Rim HWANG
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Publication number: 20180346851Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a material layer over a substrate; forming a material pattern by etching the material layer, the etching providing an etch residue on sidewalls of the material pattern; and removing the etch residue, wherein removing of the etch residue includes performing a cleaning process using a cleaning composition including water and a fluorine-containing compound or an amine, and having a pH in a range of 7 to 14.Type: ApplicationFiled: March 1, 2018Publication date: December 6, 2018Inventors: Ok-Min Moon, Sang-Soo Kim, Eung-Rim Hwang, Jong-Young Cho
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Patent number: 10042767Abstract: An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.Type: GrantFiled: March 14, 2017Date of Patent: August 7, 2018Assignee: SK hynix Inc.Inventors: Jong-Young Cho, Eung-Rim Hwang, In-Hoe Kim, Young-Min Na, Gwang-Won Lee
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Publication number: 20180018263Abstract: An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.Type: ApplicationFiled: March 14, 2017Publication date: January 18, 2018Inventors: Jong-Young CHO, Eung-Rim HWANG, In-Hoe KIM, Young-Min NA, Gwang-Won LEE
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Patent number: 7338864Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.Type: GrantFiled: March 20, 2006Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventors: Eung-Rim Hwang, Se-Aug Jang, Tae-Woo Jung, Seo-Min Kim, Woo-Jin Kim, Hyung-Soon Park, Young-Bog Kim, Hong-Seon Yang, Hyun-Chul Sohn
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Publication number: 20060160286Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.Type: ApplicationFiled: March 20, 2006Publication date: July 20, 2006Inventors: Eung-Rim Hwang, Se-Aug Jang, Tae-Woo Jung, Seo-Min Kim, Woo-Jin Kim, Hyung-Soon Park, Young-Bog Kim, Hong-Seon Yang, Hyun-Chul Sohn
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Patent number: 7045846Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.Type: GrantFiled: February 7, 2005Date of Patent: May 16, 2006Assignee: Hynix Semiconductor Inc.Inventors: Se-Aug Jang, Tae-Woo Jung, Seo-Min Kim, Woo-Jin Kim, Hyung-Soon Park, Young-Bog Kim, Hong-Seon Yang, Hyun-Chul Sohn, Eung-Rim Hwang
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Publication number: 20060022249Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.Type: ApplicationFiled: February 7, 2005Publication date: February 2, 2006Inventors: Se-Aug Jang, Tae-Woo Jung, Seo-Min Kim, Woo-Jin Kim, Hyung-Soon Park, Young-Bog Kim, Hong-Seon Yang, Hyun-Chul Sohn, Eung-Rim Hwang