Patents by Inventor Eungnak Han

Eungnak Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10459338
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Eungnak Han, Swaminathan Sivakumar, Ernisse S. Putna
  • Publication number: 20190318958
    Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.
    Type: Application
    Filed: September 30, 2016
    Publication date: October 17, 2019
    Inventors: Robert L. BRISTOL, Kevin L. LIN, James M. BLACKWELL, Rami HOURANI, Eungnak HAN
  • Publication number: 20190189500
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC
  • Publication number: 20190146335
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 16, 2019
    Inventors: James M. BLACKWELL, Robert L. BRISTOL, Marie KRYSAK, Florian GSTREIN, Eungnak HAN, Kevin L. LIN, Rami HOURANI, Shane M. HARLSON
  • Patent number: 10269622
    Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Rami Hourani, Michael J. Leeson, Todd R. Younkin, Eungnak Han, Robert L. Bristol
  • Patent number: 10256141
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
  • Publication number: 20190013246
    Abstract: Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.
    Type: Application
    Filed: March 28, 2016
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Charles H. WALLACE, Manish CHANDHOK, Paul A NYHUS, Eungnak HAN, Stephanie A. BOJARSKI, Florian GSTREIN, Gurpreet SINGH
  • Publication number: 20180323078
    Abstract: A method including forming a target pattern of a target material on a surface of a substrate; depositing a block copolymer on the surface of the substrate, wherein one of two blocks of the block copolymer preferentially aligns to the target material and the two blocks self assemble after deposition into repeating lamellar bodies on the surface of the substrate; selectively retaining one of the two blocks of the block copolymer over the other as a polymer pattern; and patterning the substrate with the polymer pattern. An apparatus including an integrated circuit substrate including a plurality of contact points and a dielectric layer on the contact points; a target pattern formed in a surface of the dielectric layer; and a self-assembled layer of repeating alternating bodies of a block copolymer, wherein one of two blocks of the block copolymer is preferentially aligned to the target pattern.
    Type: Application
    Filed: December 24, 2015
    Publication date: November 8, 2018
    Inventors: Stephanie A. BOJARSKI, Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Kranthi Kumar ELINENI, Ashish N. GAIKWAD, Paul A. NYHUS, Charles H. WALLACE, Hui Jae YOO
  • Publication number: 20180323104
    Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 8, 2018
    Applicant: Intel Corporation
    Inventors: Todd R. YOUNKIN, Eungnak HAN, Shane M. HARLSON, James M. BLACKWELL
  • Patent number: 10109583
    Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Manish Chandhok, Jasmeet S. Chawla, Florian Gstrein, Eungnak Han, Rami Hourani, Kevin Lin, Richard E. Schenker, Todd R. Younkin
  • Publication number: 20180204760
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Application
    Filed: September 23, 2015
    Publication date: July 19, 2018
    Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. (JZ) CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC
  • Publication number: 20170345643
    Abstract: Photodefinable alignment layers for chemical assisted patterning and approaches for forming photodefinable alignment layers for chemical assisted patterning are described. An embodiment of the invention may include disposing a chemically amplified resist (CAR) material over a hardmask that includes a switch component. The CAR material may then be exposed to form exposed resist portions. The exposure may produces acid in the exposed portions of the CAR material that interact with the switch component to form modified regions of the hardmask material below the exposed resist portions.
    Type: Application
    Filed: December 24, 2014
    Publication date: November 30, 2017
    Inventors: Todd R. YOUNKIN, Michael J. LEESON, James M. BLACKWELL, Ernisse S. PUTNA, Marie KRYSAK, Rami HOURANI, Eungnak HAN, Robert L. BRISTOL
  • Publication number: 20170263496
    Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.
    Type: Application
    Filed: December 24, 2014
    Publication date: September 14, 2017
    Inventors: RAMI HOURANI, MICHAEL J. LEESON, TODD R. YOUNKIN, EUNGNAK HAN, ROBERT L. BRISTOL
  • Publication number: 20170263551
    Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.
    Type: Application
    Filed: December 24, 2014
    Publication date: September 14, 2017
    Inventors: ROBERT L. BRISTOL, MANISH CHANDHOK, JASMEET S. CHAWLA, FLORIAN GSTREIN, EUNGNAK HAN, RAMI HOURANI, KEVIN LIN, RICHARD E. SCHENKER, TODD R. YOUNKIN
  • Publication number: 20170207116
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Inventors: Paul A. Nyhus, Eungnak Han, Swaminathan Sivakumar, Ernisse S. Putna
  • Patent number: 9625815
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Eungnak Han, Swaminathan Sivakumar, Ernisse S. Putna
  • Patent number: 9570349
    Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Rami Hourani, Eungnak Han, James M. Blackwell
  • Patent number: 9530733
    Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, James M. Blackwell, Scott B. Clendenning, Florian Gstrein, Eungnak Han, Grant M. Kloster, Jeanette M. Roberts, Patricio E. Romero, Rami Hourani
  • Publication number: 20160351449
    Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 1, 2016
    Inventors: Robert L. BRISTOL, Rami HOURANI, Eungnak HAN, James M. BLACKWELL
  • Patent number: 9418888
    Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Rami Hourani, Eungnak Han, James M. Blackwell