Abstract: A system and a method, the method includes determining or receiving a multiple iteration printing scheme indicative of multiple printing iterations of a coating material to be applied on an electrical circuit that comprises at least one three dimensional structure to be coated by the coating material; wherein the multiple iteration printing scheme is responsive to a shape and size of the at least one three dimensional structure; and performing multiple printing iterations of the coating material, according to the multiple iteration printing scheme; wherein at least one printing iteration is followed by at least partially curing the coating material printed during the at least one printing iteration.

Abstract: A method for printing onto a printed circuit board comprising: ink jet printing a curable ink onto said printed circuit board, ultraviolet curing of the curable ink; and curing the curable ink with thermal energy; wherein the curable ink comprises a mixture of reactive monomers and oligomers; at least one pigment; at least one photo initiator; and at least one resin out of phenolic resin, amino resin and epoxy resin.

Abstract: A method for printing a curable ink, the curable ink comprises a mixture of reactive monomers and oligomers; at least one pigment; at least one photo initiator; and at least a resin out of phenolic resin, amino resin and epoxy resin.

Abstract: A method for achieving a clean substrate, the method may include depositing a protective material on an area of a substrate, to prevent the area from being contaminated by a coating material that is to be deposited during a deposition process; and removing the protective material from the area after the coating material was cured.

Abstract: A method for printing a pattern on a electrical circuit, the method includes jetting on the electrical circuit an ultraviolet curable ink to form a pattern; and at least partially curing the ultraviolet curable ink by exposing the pattern to ultraviolet radiation generated from at least one ultraviolet light emitting diode (LED).

Abstract: A system and a method, the method includes determining or receiving a multiple iteration printing scheme indicative of multiple printing iterations of a coating material to be applied on an electrical circuit that comprises at least one three dimensional structure to be coated by the coating material; wherein the multiple iteration printing scheme is responsive to a shape and size of the at least one three dimensional structure; and performing multiple printing iterations of the coating material, according to the multiple iteration printing scheme; wherein at least one printing iteration is followed by at least partially curing the coating material printed during the at least one printing iteration.

Abstract: A method and a system for printing patterns on an object, is provided. The system may include a copper protective coating printing unit arranged to print copper protective coating ink on the object to provide at least one copper protective coating ink pattern. The system may include zero or more additional printing units selected out of a solder mask printing unit arranged to print solder mask ink on the object to provide at least one solder mask pattern and a notation mark printing unit arranged to print notation mark ink on the object to provide at least one notation mark pattern. The system also includes at least one curing unit arranged to cure each ink printed by each printing unit.

Abstract: A method of fabricating a free standing membrane including via array in a dielectric for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing laminated array, followed by terminating.

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract: A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating laye

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract: A method of fabricating a free standing membrane comprising a via array in a dielectric for use as a precursor in the construction of superior electronic support structures, comprising the stages: I—Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier, and II—Detaching the membrane from the sacrificial carrier to form a free standing laminated array, and a method of fabricating an electronic substrate based on such a membrane comprising at least the stages of: (I) Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier; (II) Detaching the membrane from the sacrificial carrier to form a free standing laminated array; (V) Thinning and planarizing, and (VII) Terminating.

Abstract: A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating laye

Abstract: A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.

Abstract: A chip carrier substrate including a lower layer and at least one upper layer of copper conductors on a base, a plurality of aluminum studs formed by anodization to be of substantially identical height which interconnect the layers of conductors, a layer of barrier metal electrically connecting the aluminum studs and the copper conductors to prevent direct contact therebetween, the aluminum studs and at least the upper layer of copper conductor being surrounded by a polymeric dielectric material, and a layer of adhesion/barrier metal beneath the upper copper conductor layer, between the upper copper conductor layer and the dielectric material.

Abstract: A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.

Abstract: A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.