Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: The present invention relates to a method for reducing data loss comprising a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme. The method further comprises a second computing step for computing the information content of the respective redundancy information entity dependent on the respective intermediate result.

Abstract: A fully synchronous servo channel for a data tape drive is provided which includes the initial acquisition of synchronous servo channel parameters, generation of a timing basis for signal interpolation, generation of a tape velocity estimate and a y-position estimate and an optimum detection of longitudinal position (LPOS) symbols embedded in servo bursts.

Abstract: A data storage device comprises a storage medium for storing data in the form of marks and at least one probe for scanning over a storage medium. The probe comprises a spring cantilever being during operation of the probe mechanically fixed to a probe holding structure, a tip with a nanoscale apex and an actuator for lateral positioning of the tip.

Abstract: The present invention relates to a method for reducing data loss comprising a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme. The method further comprises a second computing step for computing the information content of the respective redundancy information entity dependent on the respective intermediate result.

Abstract: A data storage device comprises a storage medium for storing data in the form of marks and at least one probe for scanning over a storage medium. The probe comprises a spring cantilever being during operation of the probe mechanically fixed to a probe holding structure, a tip with a nanoscale apex and an actuator for lateral positioning of the tip.

Abstract: A fully synchronous servo channel for a data type drive is provided which includes the initial acquisition of synchronous servo channel parameters, generation of a timing basis for signal interpolation, generation of a tape velocity estimate and a y-position estimate and an optimum detection of longitudinal position (LPOS) symbols embedded in servo bursts.

Abstract: A method for operating plurality of DSL modem transmitters integrated within a circuit card. The method includes each DSL modem transmitter: generating a full power physical frame when the DSL modem transmitter is provided with data to transmit; generating a low power physical frame having a control channel signal component and no data; and selecting between the full power physical frame and the low power physical frame for transmission from the DSL modem transmitter, wherein selection of the low power physical frame for transmission from the DSL modem transmitter is based only on the DSL modem transmitter having no data to transmit. The method further includes limiting aggregate flow of data to the plurality of DSL modem transmitters such that a total power required by the plurality of DSL modem transmitters is held below a predefined target power level.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method provides error-tolerance by exploiting the inherent parallelism of the probe storage array. A user data block to be written to the A-field array is first coded to produce a plurality of C-byte codewords, such that r.C=k1.A where r is the number of codewords and k1 is an integer?1. A sub-blocks of k1 bytes are produced from the codewords by selecting successive bytes of each sub-block cyclically from the r codewords. The A sub-blocks are then written via respective probes to the corresponding storage fields of the storage field array.

Abstract: A probe-based data storage device includes a storage surface having an array of A storage fields; a probe array comprising A probes for writing data to respective storage fields; and an apparatus for controlling writing of blocks of user data in the array of storage fields.

Abstract: Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method provides error-tolerance by exploiting the inherent parallelism of the probe storage array. A user data block to be written to the A-field array is first coded to produce a plurality of C-byte codewords, such that r.C=k1A where r is the number of codewords and k1 is an integer greater than or equal to 1. A sub-blocks of k1 bytes are produced from the codewords by selecting successive bytes of each sub-block cyclically from the r codewords. The A sub-blocks are then written via respective probes to the corresponding storage fields of the storage field array.

Abstract: A fully synchronous servo channel for a data tape drive is provided which includes the initial acquisition of synchronous servo channel parameters, generation of a timing basis for signal interpolation, generation of a tape velocity estimate and a y-position estimate and an optimum detection of longitudinal position (LPOS) symbols embedded in servo bursts.