Patents by Inventor Evangelos S. Eleftheriou

Evangelos S. Eleftheriou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017292
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10949735
    Abstract: A resistive memory cell is connected in circuitry which has a first input terminal for applying neuron input signals including a read portion and a write portion. The circuitry includes a read circuit producing a read signal dependent on resistance of the memory cell, and an output terminal providing a neuron output signal, dependent on the read signal in a first state of the memory cell. The circuitry also includes a storage circuit storing a measurement signal dependent on the read signal, and a switch set operable to supply the read signal to the storage circuit during application of the read portion of each neuron input signal to the memory cell, and, after application of the read portion, to apply the measurement signal in the apparatus to enable resetting of the memory cell to a second state.
    Type: Grant
    Filed: June 9, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Evangelos S. Eleftheriou, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10740004
    Abstract: A computer program product is provided for efficiently managing storage in a multi-tiered storage system. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to receive a command from an application, where the command is directed to at least one object. The program instructions are further executable by the processor to cause the processor to determine storage for the at least one object in a multi-tiered storage system based on the command, and store the at least one object in accordance with the determined storage.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert B. Basham, Joseph W. Dain, Evangelos S. Eleftheriou, Dean Hildebrand, Stan Li, Edward H. W. Lin, Harold J. Roberson, II, Slavisa Sarafijanovic, Thomas D. Weigold
  • Patent number: 10482032
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Publication number: 20190294952
    Abstract: A resistive memory cell is connected in circuitry which has a first input terminal for applying neuron input signals including a read portion and a write portion. The circuitry includes a read circuit producing a read signal dependent on resistance of the memory cell, and an output terminal providing a neuron output signal, dependent on the read signal in a first state of the memory cell. The circuitry also includes a storage circuit storing a measurement signal dependent on the read signal, and a switch set operable to supply the read signal to the storage circuit during application of the read portion of each neuron input signal to the memory cell, and, after application of the read portion, to apply the measurement signal in the apparatus to enable resetting of the memory cell to a second state.
    Type: Application
    Filed: June 9, 2019
    Publication date: September 26, 2019
    Inventors: Evangelos S. Eleftheriou, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10423878
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Publication number: 20190272464
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Application
    Filed: April 18, 2019
    Publication date: September 5, 2019
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10318861
    Abstract: A resistive memory cell is connected in circuitry which has a first input terminal for applying neuron input signals including a read portion and a write portion. The circuitry includes a read circuit producing a read signal dependent on resistance of the memory cell, and an output terminal providing a neuron output signal, dependent on the read signal in a first state of the memory cell. The circuitry also includes a storage circuit storing a measurement signal dependent on the read signal, and a switch set operable to supply the read signal to the storage circuit during application of the read portion of each neuron input signal to the memory cell, and, after application of the read portion, to apply the measurement signal in the apparatus to enable resetting of the memory cell to a second state.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10282657
    Abstract: A neuromorphic synapse with a resistive memory cell connected in circuitry having first and second input terminals. The input terminals respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry includes an output terminal for providing a synaptic output signal which is dependent on resistance of the memory cell. The circuitry is configured such that the synaptic output signal is provided at the output terminal in response to application at the first input terminal of the read portion of the pre-neuron action signal, and such that a programming signal, for programming resistance of the memory cell, is applied to the cell in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals respectively. The synapse can be adapted for operation with identical pre-neuron and post-neuron action signals.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Angeliki Pantazi, Abu Sebastian, Evangelos S. Eleftheriou, Tomas Tuma
  • Patent number: 10268949
    Abstract: Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Angeliki Pantazi, Abu Sebastian, Milos Stanisavljevic, Tomas Tuma
  • Patent number: 10217046
    Abstract: A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10152423
    Abstract: The population of data to be admitted into secondary data storage cache of a data storage system is controlled by determining heat metrics of data of the data storage system. If candidate data is submitted for admission into the secondary cache, data is selected to tentatively be evicted from the secondary cache; candidate data provided to the secondary data storage cache is rejected if its heat metric is less than the heat metric of the tentatively evicted data; and candidate data submitted for admission to the secondary data storage cache is admitted if its heat metric is equal to or greater than the heat metric of the tentatively evicted data.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Ioannis Koltsidas, Roman A. Pletka
  • Patent number: 10114613
    Abstract: A computing system includes computational memory and digital combinational circuitry operatively coupled with the computational memory. The computational memory is configured to perform computations at a prescribed precision. The digital combinational circuitry is configured to increase the precision of the computations performed by the computational memory. The computational memory and the digital combinational circuitry may be configured to iteratively perform a computation to a predefined precision. The computational memory may include circuitry configured to perform analog computation using values stored in the computational memory, and the digital combinational circuitry may include a central processing unit, a graphics processing unit and/or application specific circuitry. The computational memory may include an array of resistive memory elements having resistance or conductance values stored therein, the respective resistance or conductance values being programmable.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Konstantinos Bekas, Alessandro Curioni, Evangelos S. Eleftheriou, Manuel Le Gallo-Bourdeau, Abu Sebastian, Tomas Tuma
  • Patent number: 10079058
    Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising of row lines, of columns lines and of junctions arranged between the row lines and the column lines. Each junction comprises a programmable resistive memory element. The device comprises a signal generator and a readout circuit. The device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements. The calibration procedure is configured to program a calibration subset of the plurality of resistive memory elements to initial conductance values and to apply a constant calibration voltage to the row lines of the calibration subset. The device is configured to read calibration current values of the column lines of the calibration subset and to derive an estimation of a conductance variation parameter from the calibration current values.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Publication number: 20180232318
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Patent number: 10042779
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Patent number: 10037803
    Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 31, 2018
    Assignee: HGST NETHERLANDS BV
    Inventors: Evangelos S. Eleftheriou, Angeliki Pantazi, Nikolaos Papandreou, Haris Pozidis, Abu Sebastian
  • Patent number: 9996793
    Abstract: Method to produce a neuromorphic synapse apparatus comprising a memelement for storing a synaptic weight, and programming logic. The memelement is adapted to exhibit a desired programming characteristic. The programming logic is responsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement to update said weight. The programming logic may be responsive to an input signal indicating an input weight-change value ?Wi, and may be adapted to generate a programming signal dependent on the input weight-change value ?Wi. The programming logic is adapted such that the programming signals exploit the programming characteristic of the memelement to provide a desired weight-dependent synaptic update efficacy.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines
    Inventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tuma Tomas
  • Patent number: 9996435
    Abstract: In one embodiment, a method of managing data includes storing a first copy of data in a solid state memory using a controller of the solid state memory, and storing a second copy of the data in a hard disk drive memory using the controller. Write requests are served substantially simultaneously at both the solid state memory and the hard disk drive memory under control of the controller. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in both the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Robert Haas, Xiao-Yu Hu, Roman A. Pletka
  • Patent number: 9990395
    Abstract: A tape drive system server includes a non-volatile memory used as a cache memory for storing data files, at least part of the cache memory comprising a first region managed using a First In First Out policy management and a second region managed using a Least Recently Used policy management; a file system interface for interacting with data files stored on a tape drive system; an interface for allowing one or more remote systems reading and writing data stored on the cache memory; the server configured to: receive from the one or more remote systems one or more write requests for writing one or more data files; interpret attributes associated to data files instructed to be written by the one or more remote systems; and store data files instructed to be written by the remote systems according to the interpreted attributes.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: June 5, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Robert Haas, Nils Haustein, Jens Jelitto, Ioannis Koltsidas, Slavisa Sarafijanovic, Alexander Saupp, Harald Seipp