Abstract: An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.

Abstract: The object of designing a magneto resistive memory such that it is as resistant as possible to magnetic stray fields, offers a longest possible retention time of the information stored, and ensures a good read signal, which is achieved by the MRAM memory cells comprising a first ferromagnetic layer or reference layer, a second ferromagnetic layer or reference layer adapted to be magnetized by an external magnetic field, and a non-magnetic or non-magnetizable intermediate layer positioned between the first and second ferromagnetic layers, wherein a ferrimagnetic assistant layer is at least partially adjacently positioned at the ferromagnetic memory layer of the MRAM memory cells, and is adapted to be mechanically coupled therewith. The present invention offers higher stability and longer retention of the information stored, and thus an improvement of the read out signal.

Abstract: An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected to one of the bit line pairs at one end. Two precharge circuits are provided. One precharge circuit is arranged on a side of the crossing location and the other precharge circuit is arranged on a side of the crossing location. The precharge circuit facing the sense amplifier is arranged at a first distance from the crossing location and at a second distance from the sense amplifier. The RC constant of the bit lines, which is effective during the precharge operation, is reduced, so that the time period required for a precharge operation is reduced.

Abstract: A memory chip having an integrated address scrambler unit that has address inputs for applying an address and can be to scramble the address in various ways depending on control bits. In addition, a memory cell array is provided, which is connected downstream of the address scrambler unit. This allows an increase in flexibility during scrambling.

Abstract: An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.

Abstract: A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.

Abstract: The device according to the invention in each case has a temperature sensor for detecting the temperatures of the memory modules, which is arranged in the memory modules. In addition, a memory control module is provided, which, in order to evaluate the temperatures, is connected to the memory modules via a measurer or means for determining the highest operating temperature of the memory modules. The memory control module is designed and can be operated such that an adaptation operation is initiated, if the highest operating temperature exceeds a specific value.

Abstract: An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected to one of the bit line pairs at one end. Two precharge circuits are provided. One precharge circuit is arranged on a side of the crossing location and the other precharge circuit is arranged on a side of the crossing location. The precharge circuit facing the sense amplifier is arranged at a first distance from the crossing location and at a second distance from the sense amplifier. The RC constant of the bit lines, which is effective during the precharge operation, is reduced, so that the time period required for a precharge operation is reduced.

Abstract: The invention relates to a semiconductor memory device having