Patents by Inventor Evelyn Napetschnig
Evelyn Napetschnig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030502Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.Type: ApplicationFiled: June 9, 2023Publication date: January 25, 2024Inventors: Christian Ranacher, Evelyn Napetschnig, Sandra Ebner, Mark Pavier, Stanislav Vitanov, Paul Frank
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Publication number: 20230395539Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
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Publication number: 20230395532Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Applicant: Infineon Technologies AGInventors: Harry Walter SAX, Johann GATTERBAUER, Wolfgang LEHNERT, Evelyn NAPETSCHNIG, Michael ROGALLI
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Patent number: 11776927Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.Type: GrantFiled: July 15, 2021Date of Patent: October 3, 2023Assignee: Infineon Technologies AGInventors: Thomas Behrens, Alexander Heinrich, Evelyn Napetschnig, Bernhard Weidgans, Catharina Wille, Christina Yeong
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Patent number: 11764176Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.Type: GrantFiled: August 12, 2021Date of Patent: September 19, 2023Assignee: Infineon Technologies AGInventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
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Patent number: 11735534Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.Type: GrantFiled: May 28, 2021Date of Patent: August 22, 2023Assignee: Infineon Technologies AGInventors: Harry Walter Sax, Johann Gatterbauer, Wolfgang Lehnert, Evelyn Napetschnig, Michael Rogalli
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Patent number: 11615963Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.Type: GrantFiled: July 10, 2020Date of Patent: March 28, 2023Assignee: Infineon Technologies AGInventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
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Patent number: 11501979Abstract: A semiconductor device and a method of producing the semiconductor device are described. The semiconductor device includes: a semiconductor substrate; a metallization layer over the semiconductor substrate; a plating over the metallization layer, the plating including NiP; a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating. The structure extends from the periphery of the plating onto the passivation. The structure includes an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.Type: GrantFiled: June 17, 2021Date of Patent: November 15, 2022Assignee: Infineon Technologies Austria AGInventors: Markus Beninger-Bina, Andreas Behrendt, Mark Harrison, Robert Hartl, Peter Imrich, Reinhard Lindner, Evelyn Napetschnig
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Patent number: 11424201Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.Type: GrantFiled: June 19, 2018Date of Patent: August 23, 2022Assignee: Infineon Technologies AGInventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
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Patent number: 11410950Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.Type: GrantFiled: September 17, 2020Date of Patent: August 9, 2022Assignee: Infineon Technologies AGInventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
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Publication number: 20220246475Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
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Publication number: 20220216173Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.Type: ApplicationFiled: July 15, 2021Publication date: July 7, 2022Applicant: Infineon Technologies AGInventors: Thomas Behrens, Alexander Heinrich, Evelyn Napetschnig, Bernhard Weidgans, Catharina Wille, Christina Yeong
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Patent number: 11367654Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.Type: GrantFiled: January 15, 2019Date of Patent: June 21, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
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Publication number: 20220059477Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.Type: ApplicationFiled: August 12, 2021Publication date: February 24, 2022Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
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Publication number: 20210375792Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.Type: ApplicationFiled: May 28, 2021Publication date: December 2, 2021Applicant: Infineon Technologies AGInventors: Harry Walter SAX, Johann GATTERBAUER, Wolfgang LEHNERT, Evelyn NAPETSCHNIG, Michael ROGALLI
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Patent number: 11069644Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.Type: GrantFiled: August 30, 2019Date of Patent: July 20, 2021Assignee: Infineon Technologies AGInventors: Thomas Behrens, Alexander Heinrich, Evelyn Napetschnig, Bernhard Weidgans, Catharina Wille, Christina Yeong
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Publication number: 20210167034Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.Type: ApplicationFiled: January 15, 2021Publication date: June 3, 2021Inventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL
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Publication number: 20210091025Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.Type: ApplicationFiled: September 17, 2020Publication date: March 25, 2021Inventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
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Patent number: 10930614Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.Type: GrantFiled: July 26, 2017Date of Patent: February 23, 2021Assignee: Infineon Technologies AGInventors: Manfred Mengel, Alexander Heinrich, Steffen Orso, Thomas Behrens, Oliver Eichinger, Lim Fong, Evelyn Napetschnig, Edmund Riedl
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Patent number: 10914018Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.Type: GrantFiled: March 12, 2019Date of Patent: February 9, 2021Assignee: Infineon Technologies AGInventors: Norbert Pielmeier, Chin Yung Lai, Swee Kah Lee, Muhammad Muhammat Sanusi, Evelyn Napetschnig, Nurfarena Othman, Siew Ching Seah