Patents by Inventor Everett L. Williams, III

Everett L. Williams, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5457702
    Abstract: A system for correcting a single bit error and detecting burst errors is provided. A check bit generator generates partition check bits and burst check bits based on a H-parity matrix data regeneration scheme which provides an a single error correction and multiple bit error detection code which is linear and has the property of self orthogonality within a subclass of self orthogonal codes exclusive of Latin square codes. These check bits provide two independent sources for ascertaining the correct value for any given data bit. An error corrector and detector takes as input the data bits and check bits and provides a corrected data bit output as well as a set of error status lines. The error corrector and detector consists of Error Corrector, error corrector/detector and Error Status modules.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: October 10, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Everett L. Williams, III, Harold L. Martin, Jien-Chung Lo