Abstract: A system and method for co-simulation of hardware and software includes determining hardware executable times, associated with each of a plurality of functions included within an application code. Estimated timing annotations, which correspond to the determined hardware executable times, are then inserted into each of the functions. The application code is compiled for simulation and the compiled application code is then executed on a host computer system. Adjustments may be made to the estimated timing annotations to evaluate potential architecture changes in either target hardware or software algorithms.

Abstract: A system and method for co-simulation of hardware and software includes determining hardware executable times, associated with each of a plurality of functions included within an application code. Estimated timing annotations, which correspond to the determined hardware executable times, are then inserted into each of the functions. The application code is compiled for simulation and the compiled application code is then executed on a host computer system. Adjustments may be made to the estimated timing annotations to evaluate potential architecture changes in either target hardware or software algorithms.

Abstract: A system for anti-lock brake and traction control has a control circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, end wheel speed determination from the square waves. The state machine algorithm tracks signal peaks and valleys and uses a dual hysteresis method of generating output transitions to capture all cycles of a signal having single cycle anomalies while rejecting noise. A single rear wheel sensor having twice the frequency of front wheel sensors for equal wheel speeds is processed twice as often as each front sensor. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits.

Abstract: A system for anti-lock brake and traction control has a control circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, and wheel speed determination from the square waves. The state machine algorithm tracks signal peaks and valleys and uses a dual hysteresis method of generating output transitions to capture all cycles of a signal having single cycle anomalies while rejecting noise. A single rear wheel sensor having twice the frequency of front wheel sensors for equal wheel speeds is processed twice as often as each front sensor. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits.

Abstract: A vehicle controller in which inputs from several wheel speed sensors are used to compute wheel speed. A redundant circuit in the controller receives the sensor input signals and computes wheel speed in a different, software intensive, way. The primary and redundantly computed wheel speeds are compared to validate the primary controller circuitry and the portion of the controller used to process compute the redundant speed signal. To additionally verify proper calculation of wheel speed, the system is tested when the vehicle is at rest by applying an artificial sensor signal to the control input and then checking to see whether the controller determined the correct wheel speed.

Abstract: A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator; holding logic and mode selection logic. In one mode of operation, a rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register, causes the previous value of the capture register to be transferred to a holding register and causes the pulse accumulator to be incremented. A read of the capture holding register causes the pulse accumulator value to be transferred to a holding register and causes the pulse accumulator to be reset. The output of the interval timer can cause an interrupt signal to be generated to request service from a central processing unit.